^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for FPGA Accelerated Function Unit (AFU) Error Reporting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2019 Intel Corporation, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Wu Hao <hao.wu@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Xiao Guangrong <guangrong.xiao@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Joseph Grecco <joe.grecco@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Enno Luebbers <enno.luebbers@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Tim Whisonant <tim.whisonant@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Ananda Ravuri <ananda.ravuri@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Mitchel Henry <henry.mitchel@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/fpga-dfl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "dfl-afu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PORT_ERROR_MASK 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PORT_ERROR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PORT_FIRST_ERROR 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PORT_MALFORMED_REQ0 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PORT_MALFORMED_REQ1 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ERROR_MASK GENMASK_ULL(63, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* mask or unmask port errors by the error mask register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static void __afu_port_err_mask(struct device *dev, bool mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) writeq(mask ? ERROR_MASK : 0, base + PORT_ERROR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static void afu_port_err_mask(struct device *dev, bool mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) mutex_lock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) __afu_port_err_mask(dev, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* clear port errors. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static int afu_port_err_clear(struct device *dev, u64 err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct platform_device *pdev = to_platform_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) void __iomem *base_err, *base_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u64 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) base_err = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) base_hdr = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) mutex_lock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * clear Port Errors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * - Check for AP6 State
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * - Halt Port by keeping Port in reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * - Set PORT Error mask to all 1 to mask errors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * - Clear all errors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * - Set Port mask to all 0 to enable errors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * - All errors start capturing new errors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * - Enable Port by pulling the port out of reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* if device is still in AP6 power state, can not clear any error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) v = readq(base_hdr + PORT_HDR_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (FIELD_GET(PORT_STS_PWR_STATE, v) == PORT_STS_PWR_STATE_AP6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) dev_err(dev, "Could not clear errors, device in AP6 state.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Halt Port by keeping Port in reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ret = __afu_port_disable(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Mask all errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) __afu_port_err_mask(dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* Clear errors if err input matches with current port errors.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) v = readq(base_err + PORT_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (v == err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) writeq(v, base_err + PORT_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) v = readq(base_err + PORT_FIRST_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) writeq(v, base_err + PORT_FIRST_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* Clear mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) __afu_port_err_mask(dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Enable the Port by clear the reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) __afu_port_enable(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static ssize_t errors_show(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u64 error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) mutex_lock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) error = readq(base + PORT_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return sprintf(buf, "0x%llx\n", (unsigned long long)error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static ssize_t errors_store(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) const char *buff, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u64 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (kstrtou64(buff, 0, &value))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ret = afu_port_err_clear(dev, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return ret ? ret : count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static DEVICE_ATTR_RW(errors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static ssize_t first_error_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u64 error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) mutex_lock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) error = readq(base + PORT_FIRST_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return sprintf(buf, "0x%llx\n", (unsigned long long)error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static DEVICE_ATTR_RO(first_error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static ssize_t first_malformed_req_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u64 req0, req1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) mutex_lock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) req0 = readq(base + PORT_MALFORMED_REQ0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) req1 = readq(base + PORT_MALFORMED_REQ1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return sprintf(buf, "0x%016llx%016llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) (unsigned long long)req1, (unsigned long long)req0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static DEVICE_ATTR_RO(first_malformed_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static struct attribute *port_err_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) &dev_attr_errors.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) &dev_attr_first_error.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) &dev_attr_first_malformed_req.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static umode_t port_err_attrs_visible(struct kobject *kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct attribute *attr, int n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct device *dev = kobj_to_dev(kobj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * sysfs entries are visible only if related private feature is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * enumerated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (!dfl_get_feature_by_id(dev, PORT_FEATURE_ID_ERROR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return attr->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) const struct attribute_group port_err_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .name = "errors",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .attrs = port_err_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .is_visible = port_err_attrs_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static int port_err_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct dfl_feature *feature)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) afu_port_err_mask(&pdev->dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static void port_err_uinit(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct dfl_feature *feature)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) afu_port_err_mask(&pdev->dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) port_err_ioctl(struct platform_device *pdev, struct dfl_feature *feature,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) case DFL_FPGA_PORT_ERR_GET_IRQ_NUM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return dfl_feature_ioctl_get_num_irqs(pdev, feature, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) case DFL_FPGA_PORT_ERR_SET_IRQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return dfl_feature_ioctl_set_irq(pdev, feature, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) dev_dbg(&pdev->dev, "%x cmd not handled", cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) const struct dfl_feature_id port_err_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {.id = PORT_FEATURE_ID_ERROR,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0,}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) const struct dfl_feature_ops port_err_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .init = port_err_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .uinit = port_err_uinit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .ioctl = port_err_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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