^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * FPGA to/from HPS Bridge Driver for Altera SoCFPGA Devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013-2016 Altera Corporation, All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Includes this patch from the mailing list:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * fpga: altera-hps2fpga: fix HPS2FPGA bridge visibility to L3 masters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Signed-off-by: Anatolij Gustschin <agust@denx.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * This driver manages bridges on a Altera SOCFPGA between the ARM host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * processor system (HPS) and the embedded FPGA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * This driver supports enabling and disabling of the configured ports, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * allows for safe reprogramming of the FPGA, assuming that the new FPGA image
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * uses the same port configuration. Bridges must be disabled before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * reprogramming the FPGA and re-enabled after the FPGA has been programmed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/fpga/fpga-bridge.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ALT_L3_REMAP_OFST 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ALT_L3_REMAP_MPUZERO_MSK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ALT_L3_REMAP_H2F_MSK 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ALT_L3_REMAP_LWH2F_MSK 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define HPS2FPGA_BRIDGE_NAME "hps2fpga"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define LWHPS2FPGA_BRIDGE_NAME "lwhps2fpga"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define FPGA2HPS_BRIDGE_NAME "fpga2hps"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct altera_hps2fpga_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct reset_control *bridge_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct regmap *l3reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned int remap_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static int alt_hps2fpga_enable_show(struct fpga_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct altera_hps2fpga_data *priv = bridge->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return reset_control_status(priv->bridge_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* The L3 REMAP register is write only, so keep a cached value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static unsigned int l3_remap_shadow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static DEFINE_SPINLOCK(l3_remap_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static int _alt_hps2fpga_enable_set(struct altera_hps2fpga_data *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* bring bridge out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ret = reset_control_deassert(priv->bridge_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ret = reset_control_assert(priv->bridge_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Allow bridge to be visible to L3 masters or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (priv->remap_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) spin_lock_irqsave(&l3_remap_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) l3_remap_shadow |= ALT_L3_REMAP_MPUZERO_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) l3_remap_shadow |= priv->remap_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) l3_remap_shadow &= ~priv->remap_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ret = regmap_write(priv->l3reg, ALT_L3_REMAP_OFST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) l3_remap_shadow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) spin_unlock_irqrestore(&l3_remap_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static int alt_hps2fpga_enable_set(struct fpga_bridge *bridge, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return _alt_hps2fpga_enable_set(bridge->priv, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static const struct fpga_bridge_ops altera_hps2fpga_br_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .enable_set = alt_hps2fpga_enable_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .enable_show = alt_hps2fpga_enable_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static struct altera_hps2fpga_data hps2fpga_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .name = HPS2FPGA_BRIDGE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .remap_mask = ALT_L3_REMAP_H2F_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static struct altera_hps2fpga_data lwhps2fpga_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .name = LWHPS2FPGA_BRIDGE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .remap_mask = ALT_L3_REMAP_LWH2F_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static struct altera_hps2fpga_data fpga2hps_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .name = FPGA2HPS_BRIDGE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static const struct of_device_id altera_fpga_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { .compatible = "altr,socfpga-hps2fpga-bridge",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .data = &hps2fpga_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { .compatible = "altr,socfpga-lwhps2fpga-bridge",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .data = &lwhps2fpga_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { .compatible = "altr,socfpga-fpga2hps-bridge",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .data = &fpga2hps_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int alt_fpga_bridge_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct altera_hps2fpga_data *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) const struct of_device_id *of_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct fpga_bridge *br;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) of_id = of_match_device(altera_fpga_of_match, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (!of_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) dev_err(dev, "failed to match device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) priv = (struct altera_hps2fpga_data *)of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) priv->bridge_reset = of_reset_control_get_exclusive_by_index(dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (IS_ERR(priv->bridge_reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) dev_err(dev, "Could not get %s reset control\n", priv->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return PTR_ERR(priv->bridge_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (priv->remap_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) priv->l3reg = syscon_regmap_lookup_by_compatible("altr,l3regs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (IS_ERR(priv->l3reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) dev_err(dev, "regmap for altr,l3regs lookup failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return PTR_ERR(priv->l3reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) priv->clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (IS_ERR(priv->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) dev_err(dev, "no clock specified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return PTR_ERR(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ret = clk_prepare_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) dev_err(dev, "could not enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (!of_property_read_u32(dev->of_node, "bridge-enable", &enable)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (enable > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) dev_warn(dev, "invalid bridge-enable %u > 1\n", enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) dev_info(dev, "%s bridge\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) (enable ? "enabling" : "disabling"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ret = _alt_hps2fpga_enable_set(priv, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) br = devm_fpga_bridge_create(dev, priv->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) &altera_hps2fpga_br_ops, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (!br) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) platform_set_drvdata(pdev, br);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ret = fpga_bridge_register(br);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static int alt_fpga_bridge_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct fpga_bridge *bridge = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct altera_hps2fpga_data *priv = bridge->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) fpga_bridge_unregister(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) MODULE_DEVICE_TABLE(of, altera_fpga_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static struct platform_driver alt_fpga_bridge_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .probe = alt_fpga_bridge_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .remove = alt_fpga_bridge_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .name = "altera_hps2fpga_bridge",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .of_match_table = of_match_ptr(altera_fpga_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) module_platform_driver(alt_fpga_bridge_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) MODULE_DESCRIPTION("Altera SoCFPGA HPS to FPGA Bridge");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) MODULE_AUTHOR("Alan Tull <atull@opensource.altera.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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