Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * FPGA to SDRAM Bridge Driver for Altera SoCFPGA Devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (C) 2013-2016 Altera Corporation, All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * This driver manages a bridge between an FPGA and the SDRAM used by the ARM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * host processor system (HPS).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * The bridge contains 4 read ports, 4 write ports, and 6 command ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * Reconfiguring these ports requires that no SDRAM transactions occur during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * reconfiguration.  The code reconfiguring the ports cannot run out of SDRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * nor can the FPGA access the SDRAM during reconfiguration.  This driver does
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * not support reconfiguring the ports.  The ports are configured by code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * running out of on chip ram before Linux is started and the configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * is passed in a handoff register in the system manager.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * This driver supports enabling and disabling of the configured ports, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * allows for safe reprogramming of the FPGA, assuming that the new FPGA image
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * uses the same port configuration.  Bridges must be disabled before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * reprogramming the FPGA and re-enabled after the FPGA has been programmed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/fpga/fpga-bridge.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define ALT_SDR_CTL_FPGAPORTRST_OFST		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_MSK	0x00003fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define ALT_SDR_CTL_FPGAPORTRST_RD_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define ALT_SDR_CTL_FPGAPORTRST_WR_SHIFT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define ALT_SDR_CTL_FPGAPORTRST_CTRL_SHIFT	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  * From the Cyclone V HPS Memory Map document:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  *   These registers are used to store handoff information between the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  *   preloader and the OS. These 8 registers can be used to store any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  *   information. The contents of these registers have no impact on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  *   the state of the HPS hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define SYSMGR_ISWGRP_HANDOFF3          (0x8C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define F2S_BRIDGE_NAME "fpga2sdram"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) struct alt_fpga2sdram_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	struct regmap *sdrctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) static int alt_fpga2sdram_enable_show(struct fpga_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	struct alt_fpga2sdram_data *priv = bridge->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	regmap_read(priv->sdrctl, ALT_SDR_CTL_FPGAPORTRST_OFST, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	return (value & priv->mask) == priv->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) static inline int _alt_fpga2sdram_enable_set(struct alt_fpga2sdram_data *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 					     bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	return regmap_update_bits(priv->sdrctl, ALT_SDR_CTL_FPGAPORTRST_OFST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 				  priv->mask, enable ? priv->mask : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static int alt_fpga2sdram_enable_set(struct fpga_bridge *bridge, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	return _alt_fpga2sdram_enable_set(bridge->priv, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) struct prop_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	char *prop_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	u32 *prop_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	u32 prop_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) static const struct fpga_bridge_ops altera_fpga2sdram_br_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	.enable_set = alt_fpga2sdram_enable_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	.enable_show = alt_fpga2sdram_enable_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) static const struct of_device_id altera_fpga_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	{ .compatible = "altr,socfpga-fpga2sdram-bridge" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) static int alt_fpga_bridge_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	struct alt_fpga2sdram_data *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	struct fpga_bridge *br;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	u32 enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	struct regmap *sysmgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	priv->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	priv->sdrctl = syscon_regmap_lookup_by_compatible("altr,sdr-ctl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	if (IS_ERR(priv->sdrctl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		dev_err(dev, "regmap for altr,sdr-ctl lookup failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		return PTR_ERR(priv->sdrctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	sysmgr = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	if (IS_ERR(sysmgr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		dev_err(dev, "regmap for altr,sys-mgr lookup failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		return PTR_ERR(sysmgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	/* Get f2s bridge configuration saved in handoff register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	regmap_read(sysmgr, SYSMGR_ISWGRP_HANDOFF3, &priv->mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	br = devm_fpga_bridge_create(dev, F2S_BRIDGE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 				     &altera_fpga2sdram_br_ops, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	if (!br)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	platform_set_drvdata(pdev, br);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	ret = fpga_bridge_register(br);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	dev_info(dev, "driver initialized with handoff %08x\n", priv->mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	if (!of_property_read_u32(dev->of_node, "bridge-enable", &enable)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		if (enable > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 			dev_warn(dev, "invalid bridge-enable %u > 1\n", enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 			dev_info(dev, "%s bridge\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 				 (enable ? "enabling" : "disabling"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			ret = _alt_fpga2sdram_enable_set(priv, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 			if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 				fpga_bridge_unregister(br);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 				return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static int alt_fpga_bridge_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	struct fpga_bridge *br = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	fpga_bridge_unregister(br);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) MODULE_DEVICE_TABLE(of, altera_fpga_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static struct platform_driver altera_fpga_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	.probe = alt_fpga_bridge_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	.remove = alt_fpga_bridge_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		.name	= "altera_fpga2sdram_bridge",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		.of_match_table = of_match_ptr(altera_fpga_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) module_platform_driver(altera_fpga_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) MODULE_DESCRIPTION("Altera SoCFPGA FPGA to SDRAM Bridge");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) MODULE_AUTHOR("Alan Tull <atull@opensource.altera.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) MODULE_LICENSE("GPL v2");