^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * FPGA Manager Driver for Altera Arria/Cyclone/Stratix CvP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 DENX Software Engineering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Anatolij Gustschin <agust@denx.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Manage Altera FPGA firmware using PCIe CvP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Firmware must be in binary "rbf" format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/fpga/fpga-mgr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CVP_BAR 0 /* BAR used for data transfer in memory mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CVP_DUMMY_WR 244 /* dummy writes to clear CvP state machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TIMEOUT_US 2000 /* CVP STATUS timeout for USERMODE polling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Vendor Specific Extended Capability Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define VSE_PCIE_EXT_CAP_ID 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define VSE_PCIE_EXT_CAP_ID_VAL 0x000b /* 16bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define VSE_CVP_STATUS 0x1c /* 32bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define VSE_CVP_STATUS_CFG_RDY BIT(18) /* CVP_CONFIG_READY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define VSE_CVP_STATUS_CFG_ERR BIT(19) /* CVP_CONFIG_ERROR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define VSE_CVP_STATUS_CVP_EN BIT(20) /* ctrl block is enabling CVP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define VSE_CVP_STATUS_USERMODE BIT(21) /* USERMODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define VSE_CVP_STATUS_CFG_DONE BIT(23) /* CVP_CONFIG_DONE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define VSE_CVP_STATUS_PLD_CLK_IN_USE BIT(24) /* PLD_CLK_IN_USE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define VSE_CVP_MODE_CTRL 0x20 /* 32bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define VSE_CVP_MODE_CTRL_CVP_MODE BIT(0) /* CVP (1) or normal mode (0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define VSE_CVP_MODE_CTRL_HIP_CLK_SEL BIT(1) /* PMA (1) or fabric clock (0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define VSE_CVP_MODE_CTRL_NUMCLKS_OFF 8 /* NUMCLKS bits offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define VSE_CVP_MODE_CTRL_NUMCLKS_MASK GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define VSE_CVP_DATA 0x28 /* 32bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define VSE_CVP_PROG_CTRL 0x2c /* 32bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define VSE_CVP_PROG_CTRL_CONFIG BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define VSE_CVP_PROG_CTRL_START_XFER BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define VSE_CVP_PROG_CTRL_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define VSE_UNCOR_ERR_STATUS 0x34 /* 32bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define VSE_UNCOR_ERR_CVP_CFG_ERR BIT(5) /* CVP_CONFIG_ERROR_LATCHED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define V1_VSEC_OFFSET 0x200 /* Vendor Specific Offset V1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* V2 Defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define VSE_CVP_TX_CREDITS 0x49 /* 8bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define V2_CREDIT_TIMEOUT_US 20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define V2_CHECK_CREDIT_US 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define V2_POLL_TIMEOUT_US 1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define V2_USER_TIMEOUT_US 500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define V1_POLL_TIMEOUT_US 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DRV_NAME "altera-cvp"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ALTERA_CVP_MGR_NAME "Altera CvP FPGA Manager"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Write block sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ALTERA_CVP_V1_SIZE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ALTERA_CVP_V2_SIZE 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* Optional CvP config error status check for debugging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static bool altera_cvp_chkcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct cvp_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct altera_cvp_conf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct fpga_manager *mgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct pci_dev *pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) void __iomem *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) void (*write_data)(struct altera_cvp_conf *conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) char mgr_name[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u8 numclks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 sent_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 vsec_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) const struct cvp_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct cvp_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) void (*switch_clk)(struct altera_cvp_conf *conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int (*clear_state)(struct altera_cvp_conf *conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int (*wait_credit)(struct fpga_manager *mgr, u32 blocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) size_t block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) int poll_time_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int user_time_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static int altera_read_config_byte(struct altera_cvp_conf *conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int where, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return pci_read_config_byte(conf->pci_dev, conf->vsec_offset + where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static int altera_read_config_dword(struct altera_cvp_conf *conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int where, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return pci_read_config_dword(conf->pci_dev, conf->vsec_offset + where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int altera_write_config_dword(struct altera_cvp_conf *conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int where, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return pci_write_config_dword(conf->pci_dev, conf->vsec_offset + where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static enum fpga_mgr_states altera_cvp_state(struct fpga_manager *mgr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct altera_cvp_conf *conf = mgr->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) altera_read_config_dword(conf, VSE_CVP_STATUS, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (status & VSE_CVP_STATUS_CFG_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return FPGA_MGR_STATE_OPERATING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (status & VSE_CVP_STATUS_CVP_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return FPGA_MGR_STATE_POWER_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return FPGA_MGR_STATE_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static void altera_cvp_write_data_iomem(struct altera_cvp_conf *conf, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) writel(val, conf->map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static void altera_cvp_write_data_config(struct altera_cvp_conf *conf, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) pci_write_config_dword(conf->pci_dev, conf->vsec_offset + VSE_CVP_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* switches between CvP clock and internal clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static void altera_cvp_dummy_write(struct altera_cvp_conf *conf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* set 1 CVP clock cycle for every CVP Data Register Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) altera_read_config_dword(conf, VSE_CVP_MODE_CTRL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) val &= ~VSE_CVP_MODE_CTRL_NUMCLKS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) val |= 1 << VSE_CVP_MODE_CTRL_NUMCLKS_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) altera_write_config_dword(conf, VSE_CVP_MODE_CTRL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) for (i = 0; i < CVP_DUMMY_WR; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) conf->write_data(conf, 0); /* dummy data, could be any value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static int altera_cvp_wait_status(struct altera_cvp_conf *conf, u32 status_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u32 status_val, int timeout_us)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) unsigned int retries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) retries = timeout_us / 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (timeout_us % 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) retries++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) altera_read_config_dword(conf, VSE_CVP_STATUS, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if ((val & status_mask) == status_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* use small usleep value to re-check and break early */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) usleep_range(10, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) } while (--retries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static int altera_cvp_chk_error(struct fpga_manager *mgr, size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct altera_cvp_conf *conf = mgr->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* STEP 10 (optional) - check CVP_CONFIG_ERROR flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ret = altera_read_config_dword(conf, VSE_CVP_STATUS, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (ret || (val & VSE_CVP_STATUS_CFG_ERR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) dev_err(&mgr->dev, "CVP_CONFIG_ERROR after %zu bytes!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * CvP Version2 Functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * Recent Intel FPGAs use a credit mechanism to throttle incoming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * bitstreams and a different method of clearing the state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static int altera_cvp_v2_clear_state(struct altera_cvp_conf *conf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* Clear the START_XFER and CVP_CONFIG bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ret = altera_read_config_dword(conf, VSE_CVP_PROG_CTRL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) dev_err(&conf->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) "Error reading CVP Program Control Register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) val &= ~VSE_CVP_PROG_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ret = altera_write_config_dword(conf, VSE_CVP_PROG_CTRL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) dev_err(&conf->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) "Error writing CVP Program Control Register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return altera_cvp_wait_status(conf, VSE_CVP_STATUS_CFG_RDY, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) conf->priv->poll_time_us);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static int altera_cvp_v2_wait_for_credit(struct fpga_manager *mgr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u32 blocks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u32 timeout = V2_CREDIT_TIMEOUT_US / V2_CHECK_CREDIT_US;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct altera_cvp_conf *conf = mgr->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ret = altera_read_config_byte(conf, VSE_CVP_TX_CREDITS, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) dev_err(&conf->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) "Error reading CVP Credit Register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* Return if there is space in FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (val - (u8)conf->sent_packets)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ret = altera_cvp_chk_error(mgr, blocks * ALTERA_CVP_V2_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) dev_err(&conf->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) "CE Bit error credit reg[0x%x]:sent[0x%x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) val, conf->sent_packets);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* Limit the check credit byte traffic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) usleep_range(V2_CHECK_CREDIT_US, V2_CHECK_CREDIT_US + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) } while (timeout--);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) dev_err(&conf->pci_dev->dev, "Timeout waiting for credit\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static int altera_cvp_send_block(struct altera_cvp_conf *conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) const u32 *data, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u32 mask, words = len / sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) int i, remainder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) for (i = 0; i < words; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) conf->write_data(conf, *data++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* write up to 3 trailing bytes, if any */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) remainder = len % sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (remainder) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) mask = BIT(remainder * 8) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) conf->write_data(conf, *data & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static int altera_cvp_teardown(struct fpga_manager *mgr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct fpga_image_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct altera_cvp_conf *conf = mgr->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* STEP 12 - reset START_XFER bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) altera_read_config_dword(conf, VSE_CVP_PROG_CTRL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) val &= ~VSE_CVP_PROG_CTRL_START_XFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) altera_write_config_dword(conf, VSE_CVP_PROG_CTRL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* STEP 13 - reset CVP_CONFIG bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) val &= ~VSE_CVP_PROG_CTRL_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) altera_write_config_dword(conf, VSE_CVP_PROG_CTRL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * STEP 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * - set CVP_NUMCLKS to 1 and then issue CVP_DUMMY_WR dummy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * writes to the HIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (conf->priv->switch_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) conf->priv->switch_clk(conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* STEP 15 - poll CVP_CONFIG_READY bit for 0 with 10us timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) ret = altera_cvp_wait_status(conf, VSE_CVP_STATUS_CFG_RDY, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) conf->priv->poll_time_us);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) dev_err(&mgr->dev, "CFG_RDY == 0 timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int altera_cvp_write_init(struct fpga_manager *mgr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct fpga_image_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct altera_cvp_conf *conf = mgr->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u32 iflags, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) iflags = info ? info->flags : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (iflags & FPGA_MGR_PARTIAL_RECONFIG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) dev_err(&mgr->dev, "Partial reconfiguration not supported.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* Determine allowed clock to data ratio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (iflags & FPGA_MGR_COMPRESSED_BITSTREAM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) conf->numclks = 8; /* ratio for all compressed images */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) else if (iflags & FPGA_MGR_ENCRYPTED_BITSTREAM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) conf->numclks = 4; /* for uncompressed and encrypted images */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) conf->numclks = 1; /* for uncompressed and unencrypted images */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* STEP 1 - read CVP status and check CVP_EN flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) altera_read_config_dword(conf, VSE_CVP_STATUS, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (!(val & VSE_CVP_STATUS_CVP_EN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) dev_err(&mgr->dev, "CVP mode off: 0x%04x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (val & VSE_CVP_STATUS_CFG_RDY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) dev_warn(&mgr->dev, "CvP already started, teardown first\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) ret = altera_cvp_teardown(mgr, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * STEP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * - set HIP_CLK_SEL and CVP_MODE (must be set in the order mentioned)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* switch from fabric to PMA clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) altera_read_config_dword(conf, VSE_CVP_MODE_CTRL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) val |= VSE_CVP_MODE_CTRL_HIP_CLK_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) altera_write_config_dword(conf, VSE_CVP_MODE_CTRL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* set CVP mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) altera_read_config_dword(conf, VSE_CVP_MODE_CTRL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) val |= VSE_CVP_MODE_CTRL_CVP_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) altera_write_config_dword(conf, VSE_CVP_MODE_CTRL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * STEP 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * - set CVP_NUMCLKS to 1 and issue CVP_DUMMY_WR dummy writes to the HIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (conf->priv->switch_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) conf->priv->switch_clk(conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (conf->priv->clear_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) ret = conf->priv->clear_state(conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) dev_err(&mgr->dev, "Problem clearing out state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) conf->sent_packets = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* STEP 4 - set CVP_CONFIG bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) altera_read_config_dword(conf, VSE_CVP_PROG_CTRL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* request control block to begin transfer using CVP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) val |= VSE_CVP_PROG_CTRL_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) altera_write_config_dword(conf, VSE_CVP_PROG_CTRL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* STEP 5 - poll CVP_CONFIG READY for 1 with timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) ret = altera_cvp_wait_status(conf, VSE_CVP_STATUS_CFG_RDY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) VSE_CVP_STATUS_CFG_RDY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) conf->priv->poll_time_us);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) dev_warn(&mgr->dev, "CFG_RDY == 1 timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * STEP 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * - set CVP_NUMCLKS to 1 and issue CVP_DUMMY_WR dummy writes to the HIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (conf->priv->switch_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) conf->priv->switch_clk(conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (altera_cvp_chkcfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) ret = altera_cvp_chk_error(mgr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) dev_warn(&mgr->dev, "CFG_RDY == 1 timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* STEP 7 - set START_XFER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) altera_read_config_dword(conf, VSE_CVP_PROG_CTRL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) val |= VSE_CVP_PROG_CTRL_START_XFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) altera_write_config_dword(conf, VSE_CVP_PROG_CTRL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* STEP 8 - start transfer (set CVP_NUMCLKS for bitstream) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (conf->priv->switch_clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) altera_read_config_dword(conf, VSE_CVP_MODE_CTRL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) val &= ~VSE_CVP_MODE_CTRL_NUMCLKS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) val |= conf->numclks << VSE_CVP_MODE_CTRL_NUMCLKS_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) altera_write_config_dword(conf, VSE_CVP_MODE_CTRL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static int altera_cvp_write(struct fpga_manager *mgr, const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct altera_cvp_conf *conf = mgr->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) size_t done, remaining, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) const u32 *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* STEP 9 - write 32-bit data from RBF file to CVP data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) data = (u32 *)buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) remaining = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) while (remaining) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* Use credit throttling if available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (conf->priv->wait_credit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) status = conf->priv->wait_credit(mgr, done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) dev_err(&conf->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) "Wait Credit ERR: 0x%x\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) len = min(conf->priv->block_size, remaining);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) altera_cvp_send_block(conf, data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) data += len / sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) done += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) remaining -= len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) conf->sent_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * STEP 10 (optional) and STEP 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * - check error flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * - loop until data transfer completed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * Config images can be huge (more than 40 MiB), so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * only check after a new 4k data block has been written.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * This reduces the number of checks and speeds up the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * configuration process.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (altera_cvp_chkcfg && !(done % SZ_4K)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) status = altera_cvp_chk_error(mgr, done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (altera_cvp_chkcfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) status = altera_cvp_chk_error(mgr, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static int altera_cvp_write_complete(struct fpga_manager *mgr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct fpga_image_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct altera_cvp_conf *conf = mgr->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) u32 mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) ret = altera_cvp_teardown(mgr, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* STEP 16 - check CVP_CONFIG_ERROR_LATCHED bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) altera_read_config_dword(conf, VSE_UNCOR_ERR_STATUS, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (val & VSE_UNCOR_ERR_CVP_CFG_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) dev_err(&mgr->dev, "detected CVP_CONFIG_ERROR_LATCHED!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* STEP 17 - reset CVP_MODE and HIP_CLK_SEL bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) altera_read_config_dword(conf, VSE_CVP_MODE_CTRL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) val &= ~VSE_CVP_MODE_CTRL_HIP_CLK_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) val &= ~VSE_CVP_MODE_CTRL_CVP_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) altera_write_config_dword(conf, VSE_CVP_MODE_CTRL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* STEP 18 - poll PLD_CLK_IN_USE and USER_MODE bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) mask = VSE_CVP_STATUS_PLD_CLK_IN_USE | VSE_CVP_STATUS_USERMODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) ret = altera_cvp_wait_status(conf, mask, mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) conf->priv->user_time_us);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) dev_err(&mgr->dev, "PLD_CLK_IN_USE|USERMODE timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static const struct fpga_manager_ops altera_cvp_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .state = altera_cvp_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .write_init = altera_cvp_write_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .write = altera_cvp_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .write_complete = altera_cvp_write_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static const struct cvp_priv cvp_priv_v1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .switch_clk = altera_cvp_dummy_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .block_size = ALTERA_CVP_V1_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .poll_time_us = V1_POLL_TIMEOUT_US,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .user_time_us = TIMEOUT_US,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static const struct cvp_priv cvp_priv_v2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .clear_state = altera_cvp_v2_clear_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .wait_credit = altera_cvp_v2_wait_for_credit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .block_size = ALTERA_CVP_V2_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .poll_time_us = V2_POLL_TIMEOUT_US,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .user_time_us = V2_USER_TIMEOUT_US,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static ssize_t chkcfg_show(struct device_driver *dev, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return snprintf(buf, 3, "%d\n", altera_cvp_chkcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static ssize_t chkcfg_store(struct device_driver *drv, const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) ret = kstrtobool(buf, &altera_cvp_chkcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static DRIVER_ATTR_RW(chkcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static int altera_cvp_probe(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) const struct pci_device_id *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static void altera_cvp_remove(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static struct pci_device_id altera_cvp_id_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) { PCI_VDEVICE(ALTERA, PCI_ANY_ID) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) MODULE_DEVICE_TABLE(pci, altera_cvp_id_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static struct pci_driver altera_cvp_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .id_table = altera_cvp_id_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .probe = altera_cvp_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .remove = altera_cvp_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static int altera_cvp_probe(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) const struct pci_device_id *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct altera_cvp_conf *conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) struct fpga_manager *mgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) int ret, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) u16 cmd, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* Discover the Vendor Specific Offset for this device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) offset = pci_find_next_ext_capability(pdev, 0, PCI_EXT_CAP_ID_VNDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (!offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) dev_err(&pdev->dev, "No Vendor Specific Offset.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * First check if this is the expected FPGA device. PCI config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * space access works without enabling the PCI device, memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * space access is enabled further down.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) pci_read_config_word(pdev, offset + VSE_PCIE_EXT_CAP_ID, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (val != VSE_PCIE_EXT_CAP_ID_VAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) dev_err(&pdev->dev, "Wrong EXT_CAP_ID value 0x%x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) pci_read_config_dword(pdev, offset + VSE_CVP_STATUS, ®val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (!(regval & VSE_CVP_STATUS_CVP_EN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) "CVP is disabled for this device: CVP_STATUS Reg 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) conf = devm_kzalloc(&pdev->dev, sizeof(*conf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (!conf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) conf->vsec_offset = offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * Enable memory BAR access. We cannot use pci_enable_device() here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * because it will make the driver unusable with FPGA devices that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * have additional big IOMEM resources (e.g. 4GiB BARs) on 32-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * platform. Such BARs will not have an assigned address range and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * pci_enable_device() will fail, complaining about not claimed BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * even if the concerned BAR is not needed for FPGA configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * at all. Thus, enable the device via PCI config space command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) pci_read_config_word(pdev, PCI_COMMAND, &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (!(cmd & PCI_COMMAND_MEMORY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) cmd |= PCI_COMMAND_MEMORY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) pci_write_config_word(pdev, PCI_COMMAND, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) ret = pci_request_region(pdev, CVP_BAR, "CVP");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) dev_err(&pdev->dev, "Requesting CVP BAR region failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) goto err_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) conf->pci_dev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) conf->write_data = altera_cvp_write_data_iomem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (conf->vsec_offset == V1_VSEC_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) conf->priv = &cvp_priv_v1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) conf->priv = &cvp_priv_v2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) conf->map = pci_iomap(pdev, CVP_BAR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (!conf->map) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) dev_warn(&pdev->dev, "Mapping CVP BAR failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) conf->write_data = altera_cvp_write_data_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) snprintf(conf->mgr_name, sizeof(conf->mgr_name), "%s @%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) ALTERA_CVP_MGR_NAME, pci_name(pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) mgr = devm_fpga_mgr_create(&pdev->dev, conf->mgr_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) &altera_cvp_ops, conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (!mgr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) goto err_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) pci_set_drvdata(pdev, mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) ret = fpga_mgr_register(mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) goto err_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) err_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (conf->map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) pci_iounmap(pdev, conf->map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) pci_release_region(pdev, CVP_BAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) err_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) cmd &= ~PCI_COMMAND_MEMORY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) pci_write_config_word(pdev, PCI_COMMAND, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static void altera_cvp_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) struct fpga_manager *mgr = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct altera_cvp_conf *conf = mgr->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) u16 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) fpga_mgr_unregister(mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (conf->map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) pci_iounmap(pdev, conf->map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) pci_release_region(pdev, CVP_BAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) pci_read_config_word(pdev, PCI_COMMAND, &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) cmd &= ~PCI_COMMAND_MEMORY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) pci_write_config_word(pdev, PCI_COMMAND, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) static int __init altera_cvp_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) ret = pci_register_driver(&altera_cvp_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) ret = driver_create_file(&altera_cvp_driver.driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) &driver_attr_chkcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) pr_warn("Can't create sysfs chkcfg file\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) static void __exit altera_cvp_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) driver_remove_file(&altera_cvp_driver.driver, &driver_attr_chkcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) pci_unregister_driver(&altera_cvp_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) module_init(altera_cvp_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) module_exit(altera_cvp_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) MODULE_AUTHOR("Anatolij Gustschin <agust@denx.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) MODULE_DESCRIPTION("Module to load Altera FPGA over CvP");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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