Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) # SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) # Makefile for the fpga framework and fpga manager drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) #
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) # Core FPGA Manager Framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) obj-$(CONFIG_FPGA)			+= fpga-mgr.o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) # FPGA Manager Drivers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) obj-$(CONFIG_FPGA_MGR_ALTERA_CVP)	+= altera-cvp.o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) obj-$(CONFIG_FPGA_MGR_ALTERA_PS_SPI)	+= altera-ps-spi.o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) obj-$(CONFIG_FPGA_MGR_ICE40_SPI)	+= ice40-spi.o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) obj-$(CONFIG_FPGA_MGR_MACHXO2_SPI)	+= machxo2-spi.o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) obj-$(CONFIG_FPGA_MGR_SOCFPGA)		+= socfpga.o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)	+= socfpga-a10.o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) obj-$(CONFIG_FPGA_MGR_STRATIX10_SOC)	+= stratix10-soc.o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) obj-$(CONFIG_FPGA_MGR_TS73XX)		+= ts73xx-fpga.o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) obj-$(CONFIG_FPGA_MGR_XILINX_SPI)	+= xilinx-spi.o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)	+= zynq-fpga.o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA)	+= zynqmp-fpga.o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) obj-$(CONFIG_ALTERA_PR_IP_CORE)         += altera-pr-ip-core.o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)    += altera-pr-ip-core-plat.o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) # FPGA Bridge Drivers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) obj-$(CONFIG_FPGA_BRIDGE)		+= fpga-bridge.o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE)	+= altera-hps2fpga.o altera-fpga2sdram.o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) obj-$(CONFIG_ALTERA_FREEZE_BRIDGE)	+= altera-freeze-bridge.o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) obj-$(CONFIG_XILINX_PR_DECOUPLER)	+= xilinx-pr-decoupler.o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) # High Level Interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) obj-$(CONFIG_FPGA_REGION)		+= fpga-region.o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) obj-$(CONFIG_OF_FPGA_REGION)		+= of-fpga-region.o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) # FPGA Device Feature List Support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) obj-$(CONFIG_FPGA_DFL)			+= dfl.o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) obj-$(CONFIG_FPGA_DFL_FME)		+= dfl-fme.o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) obj-$(CONFIG_FPGA_DFL_FME_MGR)		+= dfl-fme-mgr.o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) obj-$(CONFIG_FPGA_DFL_FME_BRIDGE)	+= dfl-fme-br.o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) obj-$(CONFIG_FPGA_DFL_FME_REGION)	+= dfl-fme-region.o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) obj-$(CONFIG_FPGA_DFL_AFU)		+= dfl-afu.o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) dfl-fme-objs := dfl-fme-main.o dfl-fme-pr.o dfl-fme-error.o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) dfl-fme-objs += dfl-fme-perf.o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o dfl-afu-dma-region.o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) dfl-afu-objs += dfl-afu-error.o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) # Drivers for FPGAs which implement DFL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) obj-$(CONFIG_FPGA_DFL_PCI)		+= dfl-pci.o