Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) # SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) # FPGA framework configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) #
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) menuconfig FPGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 	tristate "FPGA Configuration Framework"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 	  Say Y here if you want support for configuring FPGAs from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 	  kernel.  The FPGA framework adds a FPGA manager class and FPGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 	  manager drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) if FPGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) config FPGA_MGR_SOCFPGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 	tristate "Altera SOCFPGA FPGA Manager"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	depends on ARCH_SOCFPGA || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	  FPGA manager driver support for Altera SOCFPGA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) config FPGA_MGR_SOCFPGA_A10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	tristate "Altera SoCFPGA Arria10"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	depends on ARCH_SOCFPGA || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	select REGMAP_MMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	  FPGA manager driver support for Altera Arria10 SoCFPGA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) config ALTERA_PR_IP_CORE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	tristate "Altera Partial Reconfiguration IP Core"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	  Core driver support for Altera Partial Reconfiguration IP component
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) config ALTERA_PR_IP_CORE_PLAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	tristate "Platform support of Altera Partial Reconfiguration IP Core"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	depends on ALTERA_PR_IP_CORE && OF && HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	  Platform driver support for Altera Partial Reconfiguration IP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	  component
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) config FPGA_MGR_ALTERA_PS_SPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	tristate "Altera FPGA Passive Serial over SPI"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	depends on SPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	select BITREVERSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	  FPGA manager driver support for Altera Arria/Cyclone/Stratix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	  using the passive serial interface over SPI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) config FPGA_MGR_ALTERA_CVP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	tristate "Altera CvP FPGA Manager"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	depends on PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	  FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	  Arria 10 and Stratix10 Altera FPGAs using the CvP interface over PCIe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) config FPGA_MGR_ZYNQ_FPGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	tristate "Xilinx Zynq FPGA"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	depends on ARCH_ZYNQ || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	  FPGA manager driver support for Xilinx Zynq FPGAs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) config FPGA_MGR_STRATIX10_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	tristate "Intel Stratix10 SoC FPGA Manager"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	depends on (ARCH_STRATIX10 && INTEL_STRATIX10_SERVICE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	  FPGA manager driver support for the Intel Stratix10 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) config FPGA_MGR_XILINX_SPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	tristate "Xilinx Configuration over Slave Serial (SPI)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	depends on SPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	  FPGA manager driver support for Xilinx FPGA configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	  over slave serial interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) config FPGA_MGR_ICE40_SPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	tristate "Lattice iCE40 SPI"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	depends on OF && SPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	  FPGA manager driver support for Lattice iCE40 FPGAs over SPI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) config FPGA_MGR_MACHXO2_SPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	tristate "Lattice MachXO2 SPI"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	depends on SPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	  FPGA manager driver support for Lattice MachXO2 configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	  over slave SPI interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) config FPGA_MGR_TS73XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	tristate "Technologic Systems TS-73xx SBC FPGA Manager"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	depends on ARCH_EP93XX && MACH_TS72XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	  FPGA manager driver support for the Altera Cyclone II FPGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	  present on the TS-73xx SBC boards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) config FPGA_BRIDGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	tristate "FPGA Bridge Framework"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	  Say Y here if you want to support bridges connected between host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	  processors and FPGAs or between FPGAs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) config SOCFPGA_FPGA_BRIDGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	tristate "Altera SoCFPGA FPGA Bridges"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	depends on ARCH_SOCFPGA && FPGA_BRIDGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	  Say Y to enable drivers for FPGA bridges for Altera SOCFPGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	  devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) config ALTERA_FREEZE_BRIDGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	tristate "Altera FPGA Freeze Bridge"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	depends on FPGA_BRIDGE && HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	  Say Y to enable drivers for Altera FPGA Freeze bridges.  A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	  freeze bridge is a bridge that exists in the FPGA fabric to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	  isolate one region of the FPGA from the busses while that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	  region is being reprogrammed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) config XILINX_PR_DECOUPLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	tristate "Xilinx LogiCORE PR Decoupler"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	depends on FPGA_BRIDGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	depends on HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	  Say Y to enable drivers for Xilinx LogiCORE PR Decoupler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	  The PR Decoupler exists in the FPGA fabric to isolate one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	  region of the FPGA from the busses while that region is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	  being reprogrammed during partial reconfig.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) config FPGA_REGION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	tristate "FPGA Region"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	depends on FPGA_BRIDGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	  FPGA Region common code.  A FPGA Region controls a FPGA Manager
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	  and the FPGA Bridges associated with either a reconfigurable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	  region of an FPGA or a whole FPGA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) config OF_FPGA_REGION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	tristate "FPGA Region Device Tree Overlay Support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	depends on OF && FPGA_REGION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	  Support for loading FPGA images by applying a Device Tree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	  overlay.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) config FPGA_DFL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	tristate "FPGA Device Feature List (DFL) support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	select FPGA_BRIDGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	select FPGA_REGION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	depends on HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	  Device Feature List (DFL) defines a feature list structure that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	  creates a linked list of feature headers within the MMIO space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	  to provide an extensible way of adding features for FPGA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	  Driver can walk through the feature headers to enumerate feature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	  devices (e.g. FPGA Management Engine, Port and Accelerator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	  Function Unit) and their private features for target FPGA devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	  Select this option to enable common support for Field-Programmable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	  Gate Array (FPGA) solutions which implement Device Feature List.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	  It provides enumeration APIs and feature device infrastructure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) config FPGA_DFL_FME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	tristate "FPGA DFL FME Driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	depends on FPGA_DFL && HWMON && PERF_EVENTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	  The FPGA Management Engine (FME) is a feature device implemented
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	  under Device Feature List (DFL) framework. Select this option to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	  enable the platform device driver for FME which implements all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	  FPGA platform level management features. There shall be one FME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	  per DFL based FPGA device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) config FPGA_DFL_FME_MGR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	tristate "FPGA DFL FME Manager Driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	depends on FPGA_DFL_FME && HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	  Say Y to enable FPGA Manager driver for FPGA Management Engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) config FPGA_DFL_FME_BRIDGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	tristate "FPGA DFL FME Bridge Driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	depends on FPGA_DFL_FME && HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	  Say Y to enable FPGA Bridge driver for FPGA Management Engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) config FPGA_DFL_FME_REGION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	tristate "FPGA DFL FME Region Driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	depends on FPGA_DFL_FME && HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	  Say Y to enable FPGA Region driver for FPGA Management Engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) config FPGA_DFL_AFU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	tristate "FPGA DFL AFU Driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	depends on FPGA_DFL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	  This is the driver for FPGA Accelerated Function Unit (AFU) which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	  implements AFU and Port management features. A User AFU connects
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	  to the FPGA infrastructure via a Port. There may be more than one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	  Port/AFU per DFL based FPGA device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) config FPGA_DFL_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	tristate "FPGA DFL PCIe Device Driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	depends on PCI && FPGA_DFL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	  Select this option to enable PCIe driver for PCIe-based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	  Field-Programmable Gate Array (FPGA) solutions which implement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	  the Device Feature List (DFL). This driver provides interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	  for userspace applications to configure, enumerate, open and access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	  FPGA accelerators on the FPGA DFL devices, enables system level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	  management functions such as FPGA partial reconfiguration, power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	  management and virtualization with DFL framework and DFL feature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	  device drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	  To compile this as a module, choose M here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) config FPGA_MGR_ZYNQMP_FPGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	tristate "Xilinx ZynqMP FPGA"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	depends on ZYNQMP_FIRMWARE || (!ZYNQMP_FIRMWARE && COMPILE_TEST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	  FPGA manager driver support for Xilinx ZynqMP FPGAs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	  This driver uses the processor configuration port(PCAP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	  to configure the programmable logic(PL) through PS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	  on ZynqMP SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) endif # FPGA