^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Trusted Foundations support for ARM CPUs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2013, NVIDIA Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/firmware/trusted_foundations.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/hardware/cache-l2x0.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/outercache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define TF_CACHE_MAINT 0xfffff100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TF_CACHE_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TF_CACHE_DISABLE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TF_CACHE_REENABLE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TF_SET_CPU_BOOT_ADDR_SMC 0xfffff200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TF_CPU_PM 0xfffffffc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TF_CPU_PM_S3 0xffffffe3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TF_CPU_PM_S2 0xffffffe6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TF_CPU_PM_S2_NO_MC_CLK 0xffffffe5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TF_CPU_PM_S1 0xffffffe4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TF_CPU_PM_S1_NOFLUSH_L2 0xffffffe7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static unsigned long tf_idle_mode = TF_PM_MODE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static unsigned long cpu_boot_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static void tf_generic_smc(u32 type, u32 arg1, u32 arg2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) register u32 r0 asm("r0") = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) register u32 r1 asm("r1") = arg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) register u32 r2 asm("r2") = arg2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) asm volatile(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) ".arch_extension sec\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) "stmfd sp!, {r4 - r11}\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) __asmeq("%0", "r0")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) __asmeq("%1", "r1")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) __asmeq("%2", "r2")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) "mov r3, #0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) "mov r4, #0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) "smc #0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) "ldmfd sp!, {r4 - r11}\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) : "r" (r0), "r" (r1), "r" (r2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) : "memory", "r3", "r12", "lr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static int tf_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) cpu_boot_addr = boot_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) tf_generic_smc(TF_SET_CPU_BOOT_ADDR_SMC, cpu_boot_addr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static int tf_prepare_idle(unsigned long mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) case TF_PM_MODE_LP0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S3, cpu_boot_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) case TF_PM_MODE_LP1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S2, cpu_boot_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) case TF_PM_MODE_LP1_NO_MC_CLK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S2_NO_MC_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) cpu_boot_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) case TF_PM_MODE_LP2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S1, cpu_boot_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) case TF_PM_MODE_LP2_NOFLUSH_L2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S1_NOFLUSH_L2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) cpu_boot_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) case TF_PM_MODE_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) tf_idle_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #ifdef CONFIG_CACHE_L2X0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static void tf_cache_write_sec(unsigned long val, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 enable_op, l2x0_way_mask = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) case L2X0_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (l2x0_saved_regs.aux_ctrl & L310_AUX_CTRL_ASSOCIATIVITY_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) l2x0_way_mask = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) switch (tf_idle_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) case TF_PM_MODE_LP2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) enable_op = TF_CACHE_REENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) enable_op = TF_CACHE_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (val == L2X0_CTRL_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) tf_generic_smc(TF_CACHE_MAINT, enable_op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) l2x0_saved_regs.aux_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) l2x0_way_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static int tf_init_cache(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) outer_cache.write_sec = tf_cache_write_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #endif /* CONFIG_CACHE_L2X0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static const struct firmware_ops trusted_foundations_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .set_cpu_boot_addr = tf_set_cpu_boot_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .prepare_idle = tf_prepare_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #ifdef CONFIG_CACHE_L2X0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .l2x0_init = tf_init_cache,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) void register_trusted_foundations(struct trusted_foundations_platform_data *pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * we are not using version information for now since currently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * supported SMCs are compatible with all TF releases
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) register_firmware_ops(&trusted_foundations_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) void of_register_trusted_foundations(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct trusted_foundations_platform_data pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) node = of_find_compatible_node(NULL, NULL, "tlm,trusted-foundations");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (!node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) err = of_property_read_u32(node, "tlm,version-major",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) &pdata.version_major);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (err != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) panic("Trusted Foundation: missing version-major property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) err = of_property_read_u32(node, "tlm,version-minor",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) &pdata.version_minor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (err != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) panic("Trusted Foundation: missing version-minor property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) register_trusted_foundations(&pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) bool trusted_foundations_registered(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return firmware_ops == &trusted_foundations_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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