^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018, NVIDIA CORPORATION.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <soc/tegra/bpmp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "bpmp-private.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define TRIGGER_OFFSET 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define RESULT_OFFSET(id) (0xc00 + id * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define TRIGGER_ID_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TRIGGER_CMD_GET 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define STA_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SET_OFFSET 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CLR_OFFSET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CH_MASK(ch) (0x3 << ((ch) * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SL_SIGL(ch) (0x0 << ((ch) * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SL_QUED(ch) (0x1 << ((ch) * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MA_FREE(ch) (0x2 << ((ch) * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MA_ACKD(ch) (0x3 << ((ch) * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct tegra210_bpmp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) void __iomem *atomics;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) void __iomem *arb_sema;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct irq_data *tx_irq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static u32 bpmp_channel_status(struct tegra_bpmp *bpmp, unsigned int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct tegra210_bpmp *priv = bpmp->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) return __raw_readl(priv->arb_sema + STA_OFFSET) & CH_MASK(index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static bool tegra210_bpmp_is_response_ready(struct tegra_bpmp_channel *channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned int index = channel->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return bpmp_channel_status(channel->bpmp, index) == MA_ACKD(index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static bool tegra210_bpmp_is_request_ready(struct tegra_bpmp_channel *channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) unsigned int index = channel->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return bpmp_channel_status(channel->bpmp, index) == SL_SIGL(index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) tegra210_bpmp_is_request_channel_free(struct tegra_bpmp_channel *channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned int index = channel->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return bpmp_channel_status(channel->bpmp, index) == MA_FREE(index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) tegra210_bpmp_is_response_channel_free(struct tegra_bpmp_channel *channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned int index = channel->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return bpmp_channel_status(channel->bpmp, index) == SL_QUED(index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static int tegra210_bpmp_post_request(struct tegra_bpmp_channel *channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct tegra210_bpmp *priv = channel->bpmp->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) __raw_writel(CH_MASK(channel->index), priv->arb_sema + CLR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static int tegra210_bpmp_post_response(struct tegra_bpmp_channel *channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct tegra210_bpmp *priv = channel->bpmp->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) __raw_writel(MA_ACKD(channel->index), priv->arb_sema + SET_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static int tegra210_bpmp_ack_response(struct tegra_bpmp_channel *channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct tegra210_bpmp *priv = channel->bpmp->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) __raw_writel(MA_ACKD(channel->index) ^ MA_FREE(channel->index),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) priv->arb_sema + CLR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static int tegra210_bpmp_ack_request(struct tegra_bpmp_channel *channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct tegra210_bpmp *priv = channel->bpmp->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) __raw_writel(SL_QUED(channel->index), priv->arb_sema + SET_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static int tegra210_bpmp_ring_doorbell(struct tegra_bpmp *bpmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct tegra210_bpmp *priv = bpmp->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct irq_data *irq_data = priv->tx_irq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * Tegra Legacy Interrupt Controller (LIC) is used to notify BPMP of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * available messages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (irq_data->chip->irq_retrigger)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return irq_data->chip->irq_retrigger(irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static irqreturn_t rx_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct tegra_bpmp *bpmp = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) tegra_bpmp_handle_rx(bpmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static int tegra210_bpmp_channel_init(struct tegra_bpmp_channel *channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct tegra_bpmp *bpmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct tegra210_bpmp *priv = bpmp->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) void *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Retrieve channel base address from BPMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) writel(index << TRIGGER_ID_SHIFT | TRIGGER_CMD_GET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) priv->atomics + TRIGGER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) address = readl(priv->atomics + RESULT_OFFSET(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) p = devm_ioremap(bpmp->dev, address, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (!p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) channel->ib = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) channel->ob = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) channel->index = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) init_completion(&channel->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) channel->bpmp = bpmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static int tegra210_bpmp_init(struct tegra_bpmp *bpmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct platform_device *pdev = to_platform_device(bpmp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct tegra210_bpmp *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) bpmp->priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) priv->atomics = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (IS_ERR(priv->atomics))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return PTR_ERR(priv->atomics);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) priv->arb_sema = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (IS_ERR(priv->arb_sema))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return PTR_ERR(priv->arb_sema);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) err = tegra210_bpmp_channel_init(bpmp->tx_channel, bpmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) bpmp->soc->channels.cpu_tx.offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) err = tegra210_bpmp_channel_init(bpmp->rx_channel, bpmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) bpmp->soc->channels.cpu_rx.offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) for (i = 0; i < bpmp->threaded.count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) unsigned int index = bpmp->soc->channels.thread.offset + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) err = tegra210_bpmp_channel_init(&bpmp->threaded_channels[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) bpmp, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) err = platform_get_irq_byname(pdev, "tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) dev_err(&pdev->dev, "failed to get TX IRQ: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) priv->tx_irq_data = irq_get_irq_data(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (!priv->tx_irq_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) dev_err(&pdev->dev, "failed to get IRQ data for TX IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) err = platform_get_irq_byname(pdev, "rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) dev_err(&pdev->dev, "failed to get rx IRQ: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) err = devm_request_irq(&pdev->dev, err, rx_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) IRQF_NO_SUSPEND, dev_name(&pdev->dev), bpmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) const struct tegra_bpmp_ops tegra210_bpmp_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .init = tegra210_bpmp_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .is_response_ready = tegra210_bpmp_is_response_ready,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .is_request_ready = tegra210_bpmp_is_request_ready,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .ack_response = tegra210_bpmp_ack_response,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .ack_request = tegra210_bpmp_ack_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .is_response_channel_free = tegra210_bpmp_is_response_channel_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .is_request_channel_free = tegra210_bpmp_is_request_channel_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .post_response = tegra210_bpmp_post_response,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .post_request = tegra210_bpmp_post_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .ring_doorbell = tegra210_bpmp_ring_doorbell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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