^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) # SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) menu "Tegra firmware driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) config TEGRA_IVC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) bool "Tegra IVC protocol"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) depends on ARCH_TEGRA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) IVC (Inter-VM Communication) protocol is part of the IPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) (Inter Processor Communication) framework on Tegra. It maintains the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) data and the different communication channels in SysRAM or RAM and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) keeps the content is synchronization between host CPU and remote
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) processors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) config TEGRA_BPMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) bool "Tegra BPMP driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) depends on ARCH_TEGRA && TEGRA_HSP_MBOX && TEGRA_IVC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) BPMP (Boot and Power Management Processor) is designed to off-loading
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) the PM functions which include clock/DVFS/thermal/power from the CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) It needs HSP as the HW synchronization and notification module and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) IVC module as the message communication protocol.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) This driver manages the IPC interface between host CPU and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) firmware running on BPMP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) endmenu