^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * it under the terms of the GNU General Public License version 2 as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 2016, Fuzhou Rockchip Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/arm-smccc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/rockchip/rockchip_sip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/cputype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #ifdef CONFIG_ARM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/psci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/smp_plat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <uapi/linux/psci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/sched/clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <soc/rockchip/rockchip_sip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PSCI_FN_NATIVE(version, name) PSCI_##version##_FN64_##name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PSCI_FN_NATIVE(version, name) PSCI_##version##_FN_##name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SIZE_PAGE(n) ((n) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static struct arm_smccc_res __invoke_sip_fn_smc(unsigned long function_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned long arg0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned long arg1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned long arg2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct arm_smccc_res res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) arm_smccc_smc(function_id, arg0, arg1, arg2, 0, 0, 0, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct arm_smccc_res sip_smc_dram(u32 arg0, u32 arg1, u32 arg2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return __invoke_sip_fn_smc(SIP_DRAM_CONFIG, arg0, arg1, arg2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) EXPORT_SYMBOL_GPL(sip_smc_dram);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct arm_smccc_res sip_smc_get_atf_version(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return __invoke_sip_fn_smc(SIP_ATF_VERSION, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) EXPORT_SYMBOL_GPL(sip_smc_get_atf_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct arm_smccc_res sip_smc_get_sip_version(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return __invoke_sip_fn_smc(SIP_SIP_VERSION, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) EXPORT_SYMBOL_GPL(sip_smc_get_sip_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) int sip_smc_set_suspend_mode(u32 ctrl, u32 config1, u32 config2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct arm_smccc_res res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) res = __invoke_sip_fn_smc(SIP_SUSPEND_MODE, ctrl, config1, config2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return res.a0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) EXPORT_SYMBOL_GPL(sip_smc_set_suspend_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct arm_smccc_res sip_smc_get_suspend_info(u32 info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct arm_smccc_res res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) res = __invoke_sip_fn_smc(SIP_SUSPEND_MODE, info, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) EXPORT_SYMBOL_GPL(sip_smc_get_suspend_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int sip_smc_virtual_poweroff(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct arm_smccc_res res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) res = __invoke_sip_fn_smc(PSCI_FN_NATIVE(1_0, SYSTEM_SUSPEND), 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return res.a0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) EXPORT_SYMBOL_GPL(sip_smc_virtual_poweroff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int sip_smc_remotectl_config(u32 func, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct arm_smccc_res res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) res = __invoke_sip_fn_smc(SIP_REMOTECTL_CFG, func, data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return res.a0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) EXPORT_SYMBOL_GPL(sip_smc_remotectl_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 sip_smc_secure_reg_read(u32 addr_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct arm_smccc_res res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) res = __invoke_sip_fn_smc(SIP_ACCESS_REG, 0, addr_phy, SECURE_REG_RD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (res.a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) pr_err("%s error: %d, addr phy: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) __func__, (int)res.a0, addr_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return res.a1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) EXPORT_SYMBOL_GPL(sip_smc_secure_reg_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int sip_smc_secure_reg_write(u32 addr_phy, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct arm_smccc_res res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) res = __invoke_sip_fn_smc(SIP_ACCESS_REG, val, addr_phy, SECURE_REG_WR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (res.a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) pr_err("%s error: %d, addr phy: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) __func__, (int)res.a0, addr_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return res.a0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) EXPORT_SYMBOL_GPL(sip_smc_secure_reg_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static void *sip_map(phys_addr_t start, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct page **pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) phys_addr_t page_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned int page_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) pgprot_t prot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) void *vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (!pfn_valid(__phys_to_pfn(start)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return ioremap(start, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) page_start = start - offset_in_page(start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) page_count = DIV_ROUND_UP(size + offset_in_page(start), PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) prot = pgprot_noncached(PAGE_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) pages = kmalloc_array(page_count, sizeof(struct page *), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (!pages) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) pr_err("%s: Failed to allocate array for %u pages\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) __func__, page_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) for (i = 0; i < page_count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) pages[i] = phys_to_page(page_start + i * PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) vaddr = vmap(pages, page_count, VM_MAP, prot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) kfree(pages);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * Since vmap() uses page granularity, we must add the offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * into the page here, to get the byte granularity address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * into the mapping to represent the actual "start" location.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return vaddr + offset_in_page(start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct arm_smccc_res sip_smc_request_share_mem(u32 page_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) share_page_type_t page_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct arm_smccc_res res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned long share_mem_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) res = __invoke_sip_fn_smc(SIP_SHARE_MEM, page_num, page_type, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (IS_SIP_ERROR(res.a0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) share_mem_phy = res.a1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) res.a1 = (unsigned long)sip_map(share_mem_phy, SIZE_PAGE(page_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) EXPORT_SYMBOL_GPL(sip_smc_request_share_mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct arm_smccc_res sip_smc_mcu_el3fiq(u32 arg0, u32 arg1, u32 arg2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return __invoke_sip_fn_smc(SIP_MCU_EL3FIQ_CFG, arg0, arg1, arg2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) EXPORT_SYMBOL_GPL(sip_smc_mcu_el3fiq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct arm_smccc_res sip_smc_vpu_reset(u32 arg0, u32 arg1, u32 arg2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct arm_smccc_res res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) res = __invoke_sip_fn_smc(PSCI_SIP_VPU_RESET, arg0, arg1, arg2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) EXPORT_SYMBOL_GPL(sip_smc_vpu_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct arm_smccc_res sip_smc_bus_config(u32 arg0, u32 arg1, u32 arg2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct arm_smccc_res res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) res = __invoke_sip_fn_smc(SIP_BUS_CFG, arg0, arg1, arg2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) EXPORT_SYMBOL_GPL(sip_smc_bus_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct dram_addrmap_info *sip_smc_get_dram_map(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct arm_smccc_res res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static struct dram_addrmap_info *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Request share memory size 4KB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) res = sip_smc_request_share_mem(1, SHARE_PAGE_TYPE_DDR_ADDRMAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (res.a0 != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) pr_err("no ATF memory for init\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) map = (struct dram_addrmap_info *)res.a1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) res = sip_smc_dram(SHARE_PAGE_TYPE_DDR_ADDRMAP, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ROCKCHIP_SIP_CONFIG_DRAM_ADDRMAP_GET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (res.a0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) pr_err("rockchip_sip_config_dram_init error:%lx\n", res.a0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) map = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) EXPORT_SYMBOL_GPL(sip_smc_get_dram_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct arm_smccc_res sip_smc_lastlog_request(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct arm_smccc_res res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) void __iomem *addr1, *addr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) res = __invoke_sip_fn_smc(SIP_LAST_LOG, local_clock(), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (IS_SIP_ERROR(res.a0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) addr1 = sip_map(res.a1, res.a3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (!addr1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) pr_err("%s: share memory buffer0 ioremap failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) res.a0 = SIP_RET_INVALID_ADDRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) addr2 = sip_map(res.a2, res.a3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (!addr2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) pr_err("%s: share memory buffer1 ioremap failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) res.a0 = SIP_RET_INVALID_ADDRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) res.a1 = (unsigned long)addr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) res.a2 = (unsigned long)addr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) EXPORT_SYMBOL_GPL(sip_smc_lastlog_request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) int sip_smc_amp_config(u32 sub_func_id, u32 arg1, u32 arg2, u32 arg3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct arm_smccc_res res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) arm_smccc_smc(RK_SIP_AMP_CFG, sub_func_id, arg1, arg2, arg3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 0, 0, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return res.a0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) EXPORT_SYMBOL_GPL(sip_smc_amp_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct arm_smccc_res sip_smc_get_amp_info(u32 sub_func_id, u32 arg1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct arm_smccc_res res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) arm_smccc_smc(RK_SIP_AMP_CFG, sub_func_id, arg1, 0, 0, 0, 0, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) EXPORT_SYMBOL_GPL(sip_smc_get_amp_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) void __iomem *sip_hdcp_request_share_memory(int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct arm_smccc_res res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (id < 0 || id >= MAX_DEVICE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) pr_err("%s: invalid device id\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* request page share memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) res = sip_smc_request_share_mem(2, SHARE_PAGE_TYPE_HDCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (IS_SIP_ERROR(res.a0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) base = (void __iomem *)res.a1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return base + id * 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct arm_smccc_res sip_hdcp_config(u32 arg0, u32 arg1, u32 arg2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct arm_smccc_res res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) res = __invoke_sip_fn_smc(SIP_HDCP_CONFIG, arg0, arg1, arg2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /************************** fiq debugger **************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * AArch32 is not allowed to call SMC64(ATF framework does not support), so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * don't change SIP_UARTDBG_FN to SIP_UARTDBG_CFG64 even when cpu is AArch32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * mode. Let ATF support SIP_UARTDBG_CFG, and we just initialize SIP_UARTDBG_FN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * depends on compile option(CONFIG_ARM or CONFIG_ARM64).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #ifdef CONFIG_ARM64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define SIP_UARTDBG_FN SIP_UARTDBG_CFG64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define SIP_UARTDBG_FN SIP_UARTDBG_CFG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static int firmware_64_32bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static int fiq_sip_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static int fiq_target_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static phys_addr_t ft_fiq_mem_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static void __iomem *ft_fiq_mem_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static void (*sip_fiq_debugger_uart_irq_tf)(struct pt_regs *_pt_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) unsigned long cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static struct pt_regs fiq_pt_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) int sip_fiq_debugger_is_enabled(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return fiq_sip_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) EXPORT_SYMBOL_GPL(sip_fiq_debugger_is_enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static void sip_fiq_debugger_get_pt_regs(void *reg_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) unsigned long sp_el1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) __maybe_unused struct sm_nsec_ctx *nsec_ctx = reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) __maybe_unused struct gp_regs_ctx *gp_regs = reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #ifdef CONFIG_ARM64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * 64-bit ATF + 64-bit kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* copy cpu context: x0 ~ spsr_el3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) memcpy(&fiq_pt_regs, reg_base, 8 * 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* copy pstate: spsr_el3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) memcpy(&fiq_pt_regs.pstate, reg_base + 0x110, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) fiq_pt_regs.sp = sp_el1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* copy pc: elr_el3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) memcpy(&fiq_pt_regs.pc, reg_base + 0x118, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (firmware_64_32bit == FIRMWARE_ATF_64BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * 64-bit ATF + 32-bit kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) fiq_pt_regs.ARM_r0 = gp_regs->x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) fiq_pt_regs.ARM_r1 = gp_regs->x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) fiq_pt_regs.ARM_r2 = gp_regs->x2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) fiq_pt_regs.ARM_r3 = gp_regs->x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) fiq_pt_regs.ARM_r4 = gp_regs->x4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) fiq_pt_regs.ARM_r5 = gp_regs->x5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) fiq_pt_regs.ARM_r6 = gp_regs->x6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) fiq_pt_regs.ARM_r7 = gp_regs->x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) fiq_pt_regs.ARM_r8 = gp_regs->x8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) fiq_pt_regs.ARM_r9 = gp_regs->x9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) fiq_pt_regs.ARM_r10 = gp_regs->x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) fiq_pt_regs.ARM_fp = gp_regs->x11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) fiq_pt_regs.ARM_ip = gp_regs->x12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) fiq_pt_regs.ARM_sp = gp_regs->x19; /* aarch32 svc_r13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) fiq_pt_regs.ARM_lr = gp_regs->x18; /* aarch32 svc_r14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) fiq_pt_regs.ARM_cpsr = gp_regs->spsr_el3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) fiq_pt_regs.ARM_pc = gp_regs->elr_el3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * 32-bit tee firmware + 32-bit kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) fiq_pt_regs.ARM_r0 = nsec_ctx->r0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) fiq_pt_regs.ARM_r1 = nsec_ctx->r1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) fiq_pt_regs.ARM_r2 = nsec_ctx->r2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) fiq_pt_regs.ARM_r3 = nsec_ctx->r3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) fiq_pt_regs.ARM_r4 = nsec_ctx->r4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) fiq_pt_regs.ARM_r5 = nsec_ctx->r5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) fiq_pt_regs.ARM_r6 = nsec_ctx->r6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) fiq_pt_regs.ARM_r7 = nsec_ctx->r7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) fiq_pt_regs.ARM_r8 = nsec_ctx->r8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) fiq_pt_regs.ARM_r9 = nsec_ctx->r9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) fiq_pt_regs.ARM_r10 = nsec_ctx->r10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) fiq_pt_regs.ARM_fp = nsec_ctx->r11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) fiq_pt_regs.ARM_ip = nsec_ctx->r12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) fiq_pt_regs.ARM_sp = nsec_ctx->svc_sp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) fiq_pt_regs.ARM_lr = nsec_ctx->svc_lr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) fiq_pt_regs.ARM_cpsr = nsec_ctx->mon_spsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * 'nsec_ctx->mon_lr' is not the fiq break point's PC, because it will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * be override as 'psci_fiq_debugger_uart_irq_tf_cb' for optee-os to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * jump to fiq_debugger handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * As 'nsec_ctx->und_lr' is not used for kernel, so optee-os uses it to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * deliver fiq break point's PC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) fiq_pt_regs.ARM_pc = nsec_ctx->und_lr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static void sip_fiq_debugger_uart_irq_tf_cb(unsigned long sp_el1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) unsigned long offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) unsigned long cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) char *cpu_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* calling fiq handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (ft_fiq_mem_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) cpu_context = (char *)ft_fiq_mem_base + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) sip_fiq_debugger_get_pt_regs(cpu_context, sp_el1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) sip_fiq_debugger_uart_irq_tf(&fiq_pt_regs, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* fiq handler done, return to EL3(then EL3 return to EL1 entry) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) __invoke_sip_fn_smc(SIP_UARTDBG_FN, 0, 0, UARTDBG_CFG_OSHDL_TO_OS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) int sip_fiq_debugger_uart_irq_tf_init(u32 irq_id, void *callback_fn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct arm_smccc_res res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) fiq_target_cpu = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* init fiq debugger callback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) sip_fiq_debugger_uart_irq_tf = callback_fn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) res = __invoke_sip_fn_smc(SIP_UARTDBG_FN, irq_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) (unsigned long)sip_fiq_debugger_uart_irq_tf_cb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) UARTDBG_CFG_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (IS_SIP_ERROR(res.a0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) pr_err("%s error: %d\n", __func__, (int)res.a0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return res.a0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* share memory ioremap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (!ft_fiq_mem_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) ft_fiq_mem_phy = res.a1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) ft_fiq_mem_base = sip_map(ft_fiq_mem_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) FIQ_UARTDBG_SHARE_MEM_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (!ft_fiq_mem_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) pr_err("%s: share memory ioremap failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) fiq_sip_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return SIP_RET_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) EXPORT_SYMBOL_GPL(sip_fiq_debugger_uart_irq_tf_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static ulong cpu_logical_map_mpidr(u32 cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #ifdef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* Empirically, local "cpu_logical_map()" for rockchip platforms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) ulong mpidr = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (cpu < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* 0x00, 0x01, 0x02, 0x03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) mpidr = cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) else if (cpu < 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /* 0x100, 0x101, 0x102, 0x103 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) mpidr = 0x100 | (cpu - 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) pr_err("Unsupported map cpu: %d\n", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return mpidr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return cpu_logical_map(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) int sip_fiq_debugger_switch_cpu(u32 cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct arm_smccc_res res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) fiq_target_cpu = cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) res = __invoke_sip_fn_smc(SIP_UARTDBG_FN, cpu_logical_map_mpidr(cpu),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 0, UARTDBG_CFG_OSHDL_CPUSW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return res.a0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) int sip_fiq_debugger_sdei_switch_cpu(u32 cur_cpu, u32 target_cpu, u32 flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) struct arm_smccc_res res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) res = __invoke_sip_fn_smc(SIP_SDEI_FIQ_DBG_SWITCH_CPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) cur_cpu, target_cpu, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return res.a0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) int sip_fiq_debugger_sdei_get_event_id(u32 *fiq, u32 *sw_cpu, u32 *flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct arm_smccc_res res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) res = __invoke_sip_fn_smc(SIP_SDEI_FIQ_DBG_GET_EVENT_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) *fiq = res.a1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) *sw_cpu = res.a2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) *flag = res.a3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return res.a0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) EXPORT_SYMBOL_GPL(sip_fiq_debugger_switch_cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) void sip_fiq_debugger_enable_debug(bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) val = enable ? UARTDBG_CFG_OSHDL_DEBUG_ENABLE :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) UARTDBG_CFG_OSHDL_DEBUG_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) __invoke_sip_fn_smc(SIP_UARTDBG_FN, 0, 0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) EXPORT_SYMBOL_GPL(sip_fiq_debugger_enable_debug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) int sip_fiq_debugger_set_print_port(u32 port_phyaddr, u32 baudrate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) struct arm_smccc_res res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) res = __invoke_sip_fn_smc(SIP_UARTDBG_FN, port_phyaddr, baudrate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) UARTDBG_CFG_PRINT_PORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return res.a0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) EXPORT_SYMBOL_GPL(sip_fiq_debugger_set_print_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) int sip_fiq_debugger_request_share_memory(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct arm_smccc_res res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /* request page share memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) res = sip_smc_request_share_mem(FIQ_UARTDBG_PAGE_NUMS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) SHARE_PAGE_TYPE_UARTDBG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (IS_SIP_ERROR(res.a0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return res.a0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) return SIP_RET_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) EXPORT_SYMBOL_GPL(sip_fiq_debugger_request_share_memory);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) int sip_fiq_debugger_get_target_cpu(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return fiq_target_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) EXPORT_SYMBOL_GPL(sip_fiq_debugger_get_target_cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) void sip_fiq_debugger_enable_fiq(bool enable, uint32_t tgt_cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) u32 en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) fiq_target_cpu = tgt_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) en = enable ? UARTDBG_CFG_FIQ_ENABEL : UARTDBG_CFG_FIQ_DISABEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) __invoke_sip_fn_smc(SIP_UARTDBG_FN, tgt_cpu, 0, en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) EXPORT_SYMBOL_GPL(sip_fiq_debugger_enable_fiq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) int sip_fiq_control(u32 sub_func, u32 irq, unsigned long data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct arm_smccc_res res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) res = __invoke_sip_fn_smc(RK_SIP_FIQ_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) sub_func, irq, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return res.a0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) EXPORT_SYMBOL_GPL(sip_fiq_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) int sip_wdt_config(u32 sub_func, u32 arg1, u32 arg2, u32 arg3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) struct arm_smccc_res res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) arm_smccc_smc(SIP_WDT_CFG, sub_func, arg1, arg2, arg3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 0, 0, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return res.a0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) EXPORT_SYMBOL_GPL(sip_wdt_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) int sip_hdcpkey_init(u32 hdcp_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct arm_smccc_res res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) res = __invoke_sip_fn_smc(TRUSTED_OS_HDCPKEY_INIT, hdcp_id, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return res.a0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) EXPORT_SYMBOL_GPL(sip_hdcpkey_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /******************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #ifdef CONFIG_ARM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static __init int sip_firmware_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) struct arm_smccc_res res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (!psci_smp_available())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * OP-TEE works on kernel 3.10 and 4.4 and we have different sip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * implement. We should tell OP-TEE the current rockchip sip version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) res = __invoke_sip_fn_smc(SIP_SIP_VERSION, SIP_IMPLEMENT_V2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) SECURE_REG_WR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (IS_SIP_ERROR(res.a0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) pr_err("%s: set rockchip sip version v2 failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * Currently, we support:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * 1. 64-bit ATF + 64-bit kernel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * 2. 64-bit ATF + 32-bit kernel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * 3. 32-bit TEE + 32-bit kernel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * We need to detect which case of above and record in firmware_64_32bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) * We get info from cpuid and compare with all supported ARMv7 cpu.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) switch (read_cpuid_part()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) case ARM_CPU_PART_CORTEX_A7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) case ARM_CPU_PART_CORTEX_A8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) case ARM_CPU_PART_CORTEX_A9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) case ARM_CPU_PART_CORTEX_A12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) case ARM_CPU_PART_CORTEX_A15:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) case ARM_CPU_PART_CORTEX_A17:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) firmware_64_32bit = FIRMWARE_TEE_32BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) firmware_64_32bit = FIRMWARE_ATF_64BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) arch_initcall(sip_firmware_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) MODULE_DESCRIPTION("Rockchip SIP Call");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags