^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Copyright (c) 2010-2015,2019 The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #ifndef __QCOM_SCM_INT_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #define __QCOM_SCM_INT_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) enum qcom_scm_convention {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) SMC_CONVENTION_UNKNOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) SMC_CONVENTION_LEGACY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) SMC_CONVENTION_ARM_32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) SMC_CONVENTION_ARM_64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) extern enum qcom_scm_convention qcom_scm_convention;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MAX_QCOM_SCM_ARGS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MAX_QCOM_SCM_RETS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) enum qcom_scm_arg_types {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) QCOM_SCM_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) QCOM_SCM_RO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) QCOM_SCM_RW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) QCOM_SCM_BUFVAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) (((a) & 0x3) << 4) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) (((b) & 0x3) << 6) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) (((c) & 0x3) << 8) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) (((d) & 0x3) << 10) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) (((e) & 0x3) << 12) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) (((f) & 0x3) << 14) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) (((g) & 0x3) << 16) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) (((h) & 0x3) << 18) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) (((i) & 0x3) << 20) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) (((j) & 0x3) << 22) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) ((num) & 0xf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * struct qcom_scm_desc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * @arginfo: Metadata describing the arguments in args[]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * @args: The array of arguments for the secure syscall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct qcom_scm_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u32 svc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u32 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u32 arginfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u64 args[MAX_QCOM_SCM_ARGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u32 owner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * struct qcom_scm_res
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * @result: The values returned by the secure syscall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct qcom_scm_res {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u64 result[MAX_QCOM_SCM_RETS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SCM_SMC_FNID(s, c) ((((s) & 0xFF) << 8) | ((c) & 0xFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) extern int __scm_smc_call(struct device *dev, const struct qcom_scm_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) enum qcom_scm_convention qcom_convention,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct qcom_scm_res *res, bool atomic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define scm_smc_call(dev, desc, res, atomic) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) __scm_smc_call((dev), (desc), qcom_scm_convention, (res), (atomic))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SCM_LEGACY_FNID(s, c) (((s) << 10) | ((c) & 0x3ff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) extern int scm_legacy_call_atomic(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) const struct qcom_scm_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct qcom_scm_res *res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) extern int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct qcom_scm_res *res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define QCOM_SCM_SVC_BOOT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define QCOM_SCM_BOOT_SET_ADDR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define QCOM_SCM_BOOT_TERMINATE_PC 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define QCOM_SCM_BOOT_SET_DLOAD_MODE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define QCOM_SCM_BOOT_SET_REMOTE_STATE 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define QCOM_SCM_FLUSH_FLAG_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define QCOM_SCM_SVC_PIL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define QCOM_SCM_PIL_PAS_INIT_IMAGE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define QCOM_SCM_PIL_PAS_MEM_SETUP 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define QCOM_SCM_PIL_PAS_AUTH_AND_RESET 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define QCOM_SCM_PIL_PAS_SHUTDOWN 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define QCOM_SCM_PIL_PAS_IS_SUPPORTED 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define QCOM_SCM_PIL_PAS_MSS_RESET 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define QCOM_SCM_SVC_IO 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define QCOM_SCM_IO_READ 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define QCOM_SCM_IO_WRITE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define QCOM_SCM_SVC_INFO 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define QCOM_SCM_INFO_IS_CALL_AVAIL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define QCOM_SCM_SVC_MP 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define QCOM_SCM_MP_RESTORE_SEC_CFG 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define QCOM_SCM_MP_VIDEO_VAR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define QCOM_SCM_MP_ASSIGN 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define QCOM_SCM_SVC_OCMEM 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define QCOM_SCM_OCMEM_LOCK_CMD 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define QCOM_SCM_OCMEM_UNLOCK_CMD 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define QCOM_SCM_SVC_ES 0x10 /* Enterprise Security */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define QCOM_SCM_ES_INVALIDATE_ICE_KEY 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define QCOM_SCM_ES_CONFIG_SET_ICE_KEY 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define QCOM_SCM_SVC_HDCP 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define QCOM_SCM_HDCP_INVOKE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define QCOM_SCM_SVC_SMMU_PROGRAM 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define QCOM_SCM_SMMU_CONFIG_ERRATA1 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) extern void __qcom_scm_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* common error codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define QCOM_SCM_V2_EBUSY -12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define QCOM_SCM_ENOMEM -5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define QCOM_SCM_EOPNOTSUPP -4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define QCOM_SCM_EINVAL_ADDR -3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define QCOM_SCM_EINVAL_ARG -2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define QCOM_SCM_ERROR -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define QCOM_SCM_INTERRUPTED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static inline int qcom_scm_remap_error(int err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) switch (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) case QCOM_SCM_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) case QCOM_SCM_EINVAL_ADDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) case QCOM_SCM_EINVAL_ARG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) case QCOM_SCM_EOPNOTSUPP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) case QCOM_SCM_ENOMEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) case QCOM_SCM_V2_EBUSY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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