^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Copyright (c) 2015,2019 The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/qcom_scm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/arm-smccc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "qcom_scm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * struct arm_smccc_args
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * @args: The array of values used in registers in smc instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct arm_smccc_args {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) unsigned long args[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static DEFINE_MUTEX(qcom_scm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define QCOM_SCM_EBUSY_WAIT_MS 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define QCOM_SCM_EBUSY_MAX_RETRY 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SCM_SMC_N_REG_ARGS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SCM_SMC_FIRST_EXT_IDX (SCM_SMC_N_REG_ARGS - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SCM_SMC_N_EXT_ARGS (MAX_QCOM_SCM_ARGS - SCM_SMC_N_REG_ARGS + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SCM_SMC_FIRST_REG_IDX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SCM_SMC_LAST_REG_IDX (SCM_SMC_FIRST_REG_IDX + SCM_SMC_N_REG_ARGS - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static void __scm_smc_do_quirk(const struct arm_smccc_args *smc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct arm_smccc_res *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned long a0 = smc->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct arm_smccc_quirk quirk = { .id = ARM_SMCCC_QUIRK_QCOM_A6 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) quirk.state.a6 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) arm_smccc_smc_quirk(a0, smc->args[1], smc->args[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) smc->args[3], smc->args[4], smc->args[5],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) quirk.state.a6, smc->args[7], res, &quirk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) if (res->a0 == QCOM_SCM_INTERRUPTED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) a0 = res->a0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) } while (res->a0 == QCOM_SCM_INTERRUPTED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static void __scm_smc_do(const struct arm_smccc_args *smc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct arm_smccc_res *res, bool atomic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) int retry_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (atomic) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) __scm_smc_do_quirk(smc, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) mutex_lock(&qcom_scm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) __scm_smc_do_quirk(smc, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) mutex_unlock(&qcom_scm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (res->a0 == QCOM_SCM_V2_EBUSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (retry_count++ > QCOM_SCM_EBUSY_MAX_RETRY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) msleep(QCOM_SCM_EBUSY_WAIT_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) } while (res->a0 == QCOM_SCM_V2_EBUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int __scm_smc_call(struct device *dev, const struct qcom_scm_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) enum qcom_scm_convention qcom_convention,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct qcom_scm_res *res, bool atomic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int arglen = desc->arginfo & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) dma_addr_t args_phys = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) void *args_virt = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) size_t alloc_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) gfp_t flag = atomic ? GFP_ATOMIC : GFP_KERNEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 smccc_call_type = atomic ? ARM_SMCCC_FAST_CALL : ARM_SMCCC_STD_CALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 qcom_smccc_convention = (qcom_convention == SMC_CONVENTION_ARM_32) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) ARM_SMCCC_SMC_32 : ARM_SMCCC_SMC_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct arm_smccc_res smc_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct arm_smccc_args smc = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) smc.args[0] = ARM_SMCCC_CALL_VAL(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) smccc_call_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) qcom_smccc_convention,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) desc->owner,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) SCM_SMC_FNID(desc->svc, desc->cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) smc.args[1] = desc->arginfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) for (i = 0; i < SCM_SMC_N_REG_ARGS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) smc.args[i + SCM_SMC_FIRST_REG_IDX] = desc->args[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (unlikely(arglen > SCM_SMC_N_REG_ARGS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) alloc_len = SCM_SMC_N_EXT_ARGS * sizeof(u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) args_virt = kzalloc(PAGE_ALIGN(alloc_len), flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (!args_virt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (qcom_smccc_convention == ARM_SMCCC_SMC_32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) __le32 *args = args_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) for (i = 0; i < SCM_SMC_N_EXT_ARGS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) args[i] = cpu_to_le32(desc->args[i +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) SCM_SMC_FIRST_EXT_IDX]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) __le64 *args = args_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) for (i = 0; i < SCM_SMC_N_EXT_ARGS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) args[i] = cpu_to_le64(desc->args[i +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) SCM_SMC_FIRST_EXT_IDX]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) args_phys = dma_map_single(dev, args_virt, alloc_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (dma_mapping_error(dev, args_phys)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) kfree(args_virt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) smc.args[SCM_SMC_LAST_REG_IDX] = args_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) __scm_smc_do(&smc, &smc_res, atomic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (args_virt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) dma_unmap_single(dev, args_phys, alloc_len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) kfree(args_virt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) res->result[0] = smc_res.a1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) res->result[1] = smc_res.a2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) res->result[2] = smc_res.a3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return (long)smc_res.a0 ? qcom_scm_remap_error(smc_res.a0) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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