Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /* Copyright (c) 2010,2015,2019 The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2015 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/qcom_scm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/arm-smccc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "qcom_scm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) static DEFINE_MUTEX(qcom_scm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * struct arm_smccc_args
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * @args:	The array of values used in registers in smc instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) struct arm_smccc_args {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	unsigned long args[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * struct scm_legacy_command - one SCM command buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * @len: total available memory for command and response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * @buf_offset: start of command buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  * @resp_hdr_offset: start of response buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  * @id: command to be executed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * @buf: buffer returned from scm_legacy_get_command_buffer()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  * An SCM command is laid out in memory as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  *	------------------- <--- struct scm_legacy_command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  *	| command header  |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  *	------------------- <--- scm_legacy_get_command_buffer()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  *	| command buffer  |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  *	------------------- <--- struct scm_legacy_response and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  *	| response header |      scm_legacy_command_to_response()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  *	------------------- <--- scm_legacy_get_response_buffer()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  *	| response buffer |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  *	-------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  * There can be arbitrary padding between the headers and buffers so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  * you should always use the appropriate scm_legacy_get_*_buffer() routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  * to access the buffers in a safe manner.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) struct scm_legacy_command {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	__le32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	__le32 buf_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	__le32 resp_hdr_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	__le32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	__le32 buf[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  * struct scm_legacy_response - one SCM response buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  * @len: total available memory for response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  * @buf_offset: start of response data relative to start of scm_legacy_response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  * @is_complete: indicates if the command has finished processing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) struct scm_legacy_response {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	__le32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	__le32 buf_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	__le32 is_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)  * scm_legacy_command_to_response() - Get a pointer to a scm_legacy_response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)  * @cmd: command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  * Returns a pointer to a response for a command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) static inline struct scm_legacy_response *scm_legacy_command_to_response(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		const struct scm_legacy_command *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	return (void *)cmd + le32_to_cpu(cmd->resp_hdr_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87)  * scm_legacy_get_command_buffer() - Get a pointer to a command buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88)  * @cmd: command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90)  * Returns a pointer to the command buffer of a command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static inline void *scm_legacy_get_command_buffer(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		const struct scm_legacy_command *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	return (void *)cmd->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)  * scm_legacy_get_response_buffer() - Get a pointer to a response buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)  * @rsp: response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)  * Returns a pointer to a response buffer of a response.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static inline void *scm_legacy_get_response_buffer(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		const struct scm_legacy_response *rsp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	return (void *)rsp + le32_to_cpu(rsp->buf_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static void __scm_legacy_do(const struct arm_smccc_args *smc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 			    struct arm_smccc_res *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		arm_smccc_smc(smc->args[0], smc->args[1], smc->args[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 			      smc->args[3], smc->args[4], smc->args[5],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 			      smc->args[6], smc->args[7], res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	} while (res->a0 == QCOM_SCM_INTERRUPTED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)  * qcom_scm_call() - Sends a command to the SCM and waits for the command to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)  * finish processing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)  * A note on cache maintenance:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)  * Note that any buffers that are expected to be accessed by the secure world
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)  * must be flushed before invoking qcom_scm_call and invalidated in the cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)  * immediately after qcom_scm_call returns. Cache maintenance on the command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)  * and response buffers is taken care of by qcom_scm_call; however, callers are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)  * responsible for any other cached buffers passed over to the secure world.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		    struct qcom_scm_res *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	u8 arglen = desc->arginfo & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	int ret = 0, context_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	struct scm_legacy_command *cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	struct scm_legacy_response *rsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	struct arm_smccc_args smc = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	struct arm_smccc_res smc_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	const size_t cmd_len = arglen * sizeof(__le32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	const size_t resp_len = MAX_QCOM_SCM_RETS * sizeof(__le32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	size_t alloc_len = sizeof(*cmd) + cmd_len + sizeof(*rsp) + resp_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	dma_addr_t cmd_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	__le32 *arg_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	const __le32 *res_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	cmd = kzalloc(PAGE_ALIGN(alloc_len), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	if (!cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	cmd->len = cpu_to_le32(alloc_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	cmd->buf_offset = cpu_to_le32(sizeof(*cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	cmd->resp_hdr_offset = cpu_to_le32(sizeof(*cmd) + cmd_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	cmd->id = cpu_to_le32(SCM_LEGACY_FNID(desc->svc, desc->cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	arg_buf = scm_legacy_get_command_buffer(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	for (i = 0; i < arglen; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		arg_buf[i] = cpu_to_le32(desc->args[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	rsp = scm_legacy_command_to_response(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	cmd_phys = dma_map_single(dev, cmd, alloc_len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	if (dma_mapping_error(dev, cmd_phys)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		kfree(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	smc.args[0] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	smc.args[1] = (unsigned long)&context_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	smc.args[2] = cmd_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	mutex_lock(&qcom_scm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	__scm_legacy_do(&smc, &smc_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	if (smc_res.a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		ret = qcom_scm_remap_error(smc_res.a0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	mutex_unlock(&qcom_scm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 					sizeof(*rsp), DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	} while (!rsp->is_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 				le32_to_cpu(rsp->buf_offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 				resp_len, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	if (res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		res_buf = scm_legacy_get_response_buffer(rsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		for (i = 0; i < MAX_QCOM_SCM_RETS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			res->result[i] = le32_to_cpu(res_buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	dma_unmap_single(dev, cmd_phys, alloc_len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	kfree(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define SCM_LEGACY_ATOMIC_N_REG_ARGS	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define SCM_LEGACY_ATOMIC_FIRST_REG_IDX	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define SCM_LEGACY_CLASS_REGISTER		(0x2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define SCM_LEGACY_MASK_IRQS		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define SCM_LEGACY_ATOMIC_ID(svc, cmd, n) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 				((SCM_LEGACY_FNID(svc, cmd) << 12) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 				SCM_LEGACY_CLASS_REGISTER | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 				SCM_LEGACY_MASK_IRQS | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 				(n & 0xf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)  * qcom_scm_call_atomic() - Send an atomic SCM command with up to 5 arguments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)  * and 3 return values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)  * @desc: SCM call descriptor containing arguments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)  * @res:  SCM call return values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)  * This shall only be used with commands that are guaranteed to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)  * uninterruptable, atomic and SMP safe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int scm_legacy_call_atomic(struct device *unused,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 			   const struct qcom_scm_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 			   struct qcom_scm_res *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	int context_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	struct arm_smccc_res smc_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	size_t arglen = desc->arginfo & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	BUG_ON(arglen > SCM_LEGACY_ATOMIC_N_REG_ARGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	arm_smccc_smc(SCM_LEGACY_ATOMIC_ID(desc->svc, desc->cmd, arglen),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		      (unsigned long)&context_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		      desc->args[0], desc->args[1], desc->args[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		      desc->args[3], desc->args[4], 0, &smc_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	if (res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		res->result[0] = smc_res.a1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		res->result[1] = smc_res.a2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		res->result[2] = smc_res.a3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	return smc_res.a0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }