^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Definitions for PCDP-defined console devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * For DIG64_HCDPv10a_01.pdf and DIG64_PCDPv20.pdf (v1.0a and v2.0 resp.),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * please see <http://www.dig64.org/specifications/>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * (c) Copyright 2002, 2004 Hewlett-Packard Development Company, L.P.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Khalid Aziz <khalid.aziz@hp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Bjorn Helgaas <bjorn.helgaas@hp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PCDP_CONSOLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PCDP_DEBUG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PCDP_CONSOLE_OUTPUT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PCDP_CONSOLE_INPUT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PCDP_UART (0 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PCDP_VGA (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PCDP_USB (2 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* pcdp_uart.type and pcdp_device.type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PCDP_CONSOLE_UART (PCDP_UART | PCDP_CONSOLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PCDP_DEBUG_UART (PCDP_UART | PCDP_DEBUG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PCDP_CONSOLE_VGA (PCDP_VGA | PCDP_CONSOLE_OUTPUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PCDP_CONSOLE_USB (PCDP_USB | PCDP_CONSOLE_INPUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* pcdp_uart.flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PCDP_UART_EDGE_SENSITIVE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PCDP_UART_ACTIVE_LOW (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PCDP_UART_PRIMARY_CONSOLE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PCDP_UART_IRQ (1 << 6) /* in pci_func for rev < 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PCDP_UART_PCI (1 << 7) /* in pci_func for rev < 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct pcdp_uart {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u8 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u8 bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u8 parity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u8 stop_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u8 pci_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u8 pci_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u8 pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u8 pci_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u64 baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct acpi_generic_address addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u16 pci_dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u16 pci_vendor_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u32 gsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u32 clock_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u8 pci_prog_intfc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u16 conout_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PCDP_IF_PCI 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* pcdp_if_pci.trans */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PCDP_PCI_TRANS_IOPORT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PCDP_PCI_TRANS_MMIO 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct pcdp_if_pci {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u8 interconnect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u16 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u8 segment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u8 bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u8 dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u8 fun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u16 dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u16 vendor_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 acpi_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u64 mmio_tra;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u64 ioport_tra;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u8 trans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct pcdp_vga {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u8 count; /* address space descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* pcdp_device.flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PCDP_PRIMARY_CONSOLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct pcdp_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u8 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u16 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u16 efi_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* next data is pcdp_if_pci or pcdp_if_acpi (not yet supported) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* next data is device specific type (currently only pcdp_vga) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct pcdp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u8 signature[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u8 rev; /* PCDP v2.0 is rev 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u8 chksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u8 oemid[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u8 oem_tabid[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 oem_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u8 creator_id[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 creator_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 num_uarts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct pcdp_uart uart[]; /* actual size is num_uarts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* remainder of table is pcdp_device structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) } __attribute__((packed));
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags