Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright 2018 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *  Author: Dong Aisheng <aisheng.dong@nxp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Implementation of the SCU IPC functions using MUs (client side).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/firmware/imx/ipc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/firmware/imx/sci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/mailbox_client.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define SCU_MU_CHAN_NUM		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define MAX_RX_TIMEOUT		(msecs_to_jiffies(30))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) struct imx_sc_chan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	struct imx_sc_ipc *sc_ipc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	struct mbox_client cl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	struct mbox_chan *ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	struct completion tx_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) struct imx_sc_ipc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	/* SCU uses 4 Tx and 4 Rx channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	struct imx_sc_chan chans[SCU_MU_CHAN_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	struct completion done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	bool fast_ipc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	/* temporarily store the SCU msg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	u32 *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	u8 rx_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	u8 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  * This type is used to indicate error response for most functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) enum imx_sc_error_codes {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	IMX_SC_ERR_NONE = 0,	/* Success */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	IMX_SC_ERR_VERSION = 1,	/* Incompatible API version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	IMX_SC_ERR_CONFIG = 2,	/* Configuration error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	IMX_SC_ERR_PARM = 3,	/* Bad parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	IMX_SC_ERR_NOACCESS = 4,	/* Permission error (no access) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	IMX_SC_ERR_LOCKED = 5,	/* Permission error (locked) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	IMX_SC_ERR_UNAVAILABLE = 6,	/* Unavailable (out of resources) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	IMX_SC_ERR_NOTFOUND = 7,	/* Not found */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	IMX_SC_ERR_NOPOWER = 8,	/* No power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	IMX_SC_ERR_IPC = 9,		/* Generic IPC error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	IMX_SC_ERR_BUSY = 10,	/* Resource is currently busy/active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	IMX_SC_ERR_FAIL = 11,	/* General I/O failure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	IMX_SC_ERR_LAST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static int imx_sc_linux_errmap[IMX_SC_ERR_LAST] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	0,	 /* IMX_SC_ERR_NONE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	-EINVAL, /* IMX_SC_ERR_VERSION */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	-EINVAL, /* IMX_SC_ERR_CONFIG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	-EINVAL, /* IMX_SC_ERR_PARM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	-EACCES, /* IMX_SC_ERR_NOACCESS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	-EACCES, /* IMX_SC_ERR_LOCKED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	-ERANGE, /* IMX_SC_ERR_UNAVAILABLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	-EEXIST, /* IMX_SC_ERR_NOTFOUND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	-EPERM,	 /* IMX_SC_ERR_NOPOWER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	-EPIPE,	 /* IMX_SC_ERR_IPC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	-EBUSY,	 /* IMX_SC_ERR_BUSY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	-EIO,	 /* IMX_SC_ERR_FAIL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) static struct imx_sc_ipc *imx_sc_ipc_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) static inline int imx_sc_to_linux_errno(int errno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	if (errno >= IMX_SC_ERR_NONE && errno < IMX_SC_ERR_LAST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		return imx_sc_linux_errmap[errno];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92)  * Get the default handle used by SCU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) int imx_scu_get_handle(struct imx_sc_ipc **ipc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	if (!imx_sc_ipc_handle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	*ipc = imx_sc_ipc_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) EXPORT_SYMBOL(imx_scu_get_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Callback called when the word of a message is ack-ed, eg read by SCU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static void imx_scu_tx_done(struct mbox_client *cl, void *mssg, int r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	struct imx_sc_chan *sc_chan = container_of(cl, struct imx_sc_chan, cl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	complete(&sc_chan->tx_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static void imx_scu_rx_callback(struct mbox_client *c, void *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	struct imx_sc_chan *sc_chan = container_of(c, struct imx_sc_chan, cl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	struct imx_sc_ipc *sc_ipc = sc_chan->sc_ipc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	struct imx_sc_rpc_msg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	u32 *data = msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	if (!sc_ipc->msg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		dev_warn(sc_ipc->dev, "unexpected rx idx %d 0x%08x, ignore!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 				sc_chan->idx, *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	if (sc_ipc->fast_ipc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		hdr = msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		sc_ipc->rx_size = hdr->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		sc_ipc->msg[0] = *data++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		for (i = 1; i < sc_ipc->rx_size; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			sc_ipc->msg[i] = *data++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		complete(&sc_ipc->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	if (sc_chan->idx == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		hdr = msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		sc_ipc->rx_size = hdr->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		dev_dbg(sc_ipc->dev, "msg rx size %u\n", sc_ipc->rx_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		if (sc_ipc->rx_size > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 			dev_warn(sc_ipc->dev, "RPC does not support receiving over 4 words: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 				 sc_ipc->rx_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	sc_ipc->msg[sc_chan->idx] = *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	sc_ipc->count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	dev_dbg(sc_ipc->dev, "mu %u msg %u 0x%x\n", sc_chan->idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		sc_ipc->count, *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	if ((sc_ipc->rx_size != 0) && (sc_ipc->count == sc_ipc->rx_size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		complete(&sc_ipc->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int imx_scu_ipc_write(struct imx_sc_ipc *sc_ipc, void *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	struct imx_sc_rpc_msg hdr = *(struct imx_sc_rpc_msg *)msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	struct imx_sc_chan *sc_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	u32 *data = msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	/* Check size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	if (hdr.size > IMX_SC_RPC_MAX_MSG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	dev_dbg(sc_ipc->dev, "RPC SVC %u FUNC %u SIZE %u\n", hdr.svc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		hdr.func, hdr.size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	size = sc_ipc->fast_ipc ? 1 : hdr.size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	for (i = 0; i < size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		sc_chan = &sc_ipc->chans[i % 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		 * SCU requires that all messages words are written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		 * sequentially but linux MU driver implements multiple
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		 * independent channels for each register so ordering between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		 * different channels must be ensured by SCU API interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		 * Wait for tx_done before every send to ensure that no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		 * queueing happens at the mailbox channel level.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		if (!sc_ipc->fast_ipc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			wait_for_completion(&sc_chan->tx_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			reinit_completion(&sc_chan->tx_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		ret = mbox_send_message(sc_chan->ch, &data[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)  * RPC command/response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int imx_scu_call_rpc(struct imx_sc_ipc *sc_ipc, void *msg, bool have_resp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	uint8_t saved_svc, saved_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	struct imx_sc_rpc_msg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	if (WARN_ON(!sc_ipc || !msg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	mutex_lock(&sc_ipc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	reinit_completion(&sc_ipc->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	if (have_resp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		sc_ipc->msg = msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		saved_svc = ((struct imx_sc_rpc_msg *)msg)->svc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		saved_func = ((struct imx_sc_rpc_msg *)msg)->func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	sc_ipc->count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	ret = imx_scu_ipc_write(sc_ipc, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		dev_err(sc_ipc->dev, "RPC send msg failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	if (have_resp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		if (!wait_for_completion_timeout(&sc_ipc->done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 						 MAX_RX_TIMEOUT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 			dev_err(sc_ipc->dev, "RPC send msg timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 			mutex_unlock(&sc_ipc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 			return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		/* response status is stored in hdr->func field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		hdr = msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		ret = hdr->func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		 * Some special SCU firmware APIs do NOT have return value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		 * in hdr->func, but they do have response data, those special
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		 * APIs are defined as void function in SCU firmware, so they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		 * should be treated as return success always.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		if ((saved_svc == IMX_SC_RPC_SVC_MISC) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 			(saved_func == IMX_SC_MISC_FUNC_UNIQUE_ID ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 			 saved_func == IMX_SC_MISC_FUNC_GET_BUTTON_STATUS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 			ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	sc_ipc->msg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	mutex_unlock(&sc_ipc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	dev_dbg(sc_ipc->dev, "RPC SVC done\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	return imx_sc_to_linux_errno(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) EXPORT_SYMBOL(imx_scu_call_rpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static int imx_scu_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	struct imx_sc_ipc *sc_ipc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	struct imx_sc_chan *sc_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	struct mbox_client *cl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	char *chan_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	struct of_phandle_args args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	int num_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	sc_ipc = devm_kzalloc(dev, sizeof(*sc_ipc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	if (!sc_ipc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	ret = of_parse_phandle_with_args(pdev->dev.of_node, "mboxes",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 					 "#mbox-cells", 0, &args);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	sc_ipc->fast_ipc = of_device_is_compatible(args.np, "fsl,imx8-mu-scu");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	num_channel = sc_ipc->fast_ipc ? 2 : SCU_MU_CHAN_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	for (i = 0; i < num_channel; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		if (i < num_channel / 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 			chan_name = kasprintf(GFP_KERNEL, "tx%d", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 			chan_name = kasprintf(GFP_KERNEL, "rx%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 					      i - num_channel / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		if (!chan_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 			return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		sc_chan = &sc_ipc->chans[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		cl = &sc_chan->cl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		cl->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		cl->tx_block = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		cl->knows_txdone = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		cl->rx_callback = imx_scu_rx_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		if (!sc_ipc->fast_ipc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 			/* Initial tx_done completion as "done" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 			cl->tx_done = imx_scu_tx_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 			init_completion(&sc_chan->tx_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 			complete(&sc_chan->tx_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		sc_chan->sc_ipc = sc_ipc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		sc_chan->idx = i % (num_channel / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		sc_chan->ch = mbox_request_channel_byname(cl, chan_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		if (IS_ERR(sc_chan->ch)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 			ret = PTR_ERR(sc_chan->ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 			if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 				dev_err(dev, "Failed to request mbox chan %s ret %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 					chan_name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 			kfree(chan_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		dev_dbg(dev, "request mbox chan %s\n", chan_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		/* chan_name is not used anymore by framework */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		kfree(chan_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	sc_ipc->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	mutex_init(&sc_ipc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	init_completion(&sc_ipc->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	imx_sc_ipc_handle = sc_ipc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	ret = imx_scu_soc_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		dev_warn(dev, "failed to initialize SoC info: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	ret = imx_scu_enable_general_irq_channel(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		dev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 			"failed to enable general irq channel: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	dev_info(dev, "NXP i.MX SCU Initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	return devm_of_platform_populate(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static const struct of_device_id imx_scu_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	{ .compatible = "fsl,imx-scu", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	{ /* Sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static struct platform_driver imx_scu_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		.name = "imx-scu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		.of_match_table = imx_scu_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	.probe = imx_scu_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) builtin_platform_driver(imx_scu_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) MODULE_AUTHOR("Dong Aisheng <aisheng.dong@nxp.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) MODULE_DESCRIPTION("IMX SCU firmware protocol driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) MODULE_LICENSE("GPL v2");