^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * UEFI Common Platform Error Record (CPER) support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/cper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/dmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/aer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/printk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <acpi/ghes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <ras/ras_event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static const char * const arm_reg_ctx_strs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) "AArch32 general purpose registers",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) "AArch32 EL1 context registers",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) "AArch32 EL2 context registers",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) "AArch32 secure context registers",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) "AArch64 general purpose registers",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) "AArch64 EL1 context registers",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) "AArch64 EL2 context registers",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) "AArch64 EL3 context registers",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) "Misc. system register structure",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static const char * const arm_err_trans_type_strs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) "Instruction",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) "Data Access",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) "Generic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static const char * const arm_bus_err_op_strs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) "Generic error (type cannot be determined)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) "Generic read (type of instruction or data request cannot be determined)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) "Generic write (type of instruction of data request cannot be determined)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) "Data read",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) "Data write",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) "Instruction fetch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) "Prefetch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static const char * const arm_cache_err_op_strs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) "Generic error (type cannot be determined)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) "Generic read (type of instruction or data request cannot be determined)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) "Generic write (type of instruction of data request cannot be determined)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) "Data read",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) "Data write",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) "Instruction fetch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) "Prefetch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) "Eviction",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) "Snooping (processor initiated a cache snoop that resulted in an error)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) "Snooped (processor raised a cache error caused by another processor or device snooping its cache)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) "Management",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static const char * const arm_tlb_err_op_strs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) "Generic error (type cannot be determined)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) "Generic read (type of instruction or data request cannot be determined)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) "Generic write (type of instruction of data request cannot be determined)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) "Data read",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) "Data write",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) "Instruction fetch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) "Prefetch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) "Local management operation (processor initiated a TLB management operation that resulted in an error)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) "External management operation (processor raised a TLB error caused by another processor or device broadcasting TLB operations)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static const char * const arm_bus_err_part_type_strs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) "Local processor originated request",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) "Local processor responded to request",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) "Local processor observed",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) "Generic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static const char * const arm_bus_err_addr_space_strs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) "External Memory Access",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) "Internal Memory Access",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) "Unknown",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) "Device Memory Access",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static void cper_print_arm_err_info(const char *pfx, u32 type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u64 error_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u8 trans_type, op_type, level, participation_type, address_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u16 mem_attributes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) bool proc_context_corrupt, corrected, precise_pc, restartable_pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) bool time_out, access_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* If the type is unknown, bail. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (type > CPER_ARM_MAX_TYPE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * Vendor type errors have error information values that are vendor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * specific.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (type == CPER_ARM_VENDOR_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (error_info & CPER_ARM_ERR_VALID_TRANSACTION_TYPE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) trans_type = ((error_info >> CPER_ARM_ERR_TRANSACTION_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) & CPER_ARM_ERR_TRANSACTION_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (trans_type < ARRAY_SIZE(arm_err_trans_type_strs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) printk("%stransaction type: %s\n", pfx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) arm_err_trans_type_strs[trans_type]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (error_info & CPER_ARM_ERR_VALID_OPERATION_TYPE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) op_type = ((error_info >> CPER_ARM_ERR_OPERATION_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) & CPER_ARM_ERR_OPERATION_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) case CPER_ARM_CACHE_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (op_type < ARRAY_SIZE(arm_cache_err_op_strs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) printk("%soperation type: %s\n", pfx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) arm_cache_err_op_strs[op_type]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) case CPER_ARM_TLB_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (op_type < ARRAY_SIZE(arm_tlb_err_op_strs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) printk("%soperation type: %s\n", pfx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) arm_tlb_err_op_strs[op_type]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) case CPER_ARM_BUS_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (op_type < ARRAY_SIZE(arm_bus_err_op_strs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) printk("%soperation type: %s\n", pfx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) arm_bus_err_op_strs[op_type]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (error_info & CPER_ARM_ERR_VALID_LEVEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) level = ((error_info >> CPER_ARM_ERR_LEVEL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) & CPER_ARM_ERR_LEVEL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) case CPER_ARM_CACHE_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) printk("%scache level: %d\n", pfx, level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) case CPER_ARM_TLB_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) printk("%sTLB level: %d\n", pfx, level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) case CPER_ARM_BUS_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) printk("%saffinity level at which the bus error occurred: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) pfx, level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (error_info & CPER_ARM_ERR_VALID_PROC_CONTEXT_CORRUPT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) proc_context_corrupt = ((error_info >> CPER_ARM_ERR_PC_CORRUPT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) & CPER_ARM_ERR_PC_CORRUPT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (proc_context_corrupt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) printk("%sprocessor context corrupted\n", pfx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) printk("%sprocessor context not corrupted\n", pfx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (error_info & CPER_ARM_ERR_VALID_CORRECTED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) corrected = ((error_info >> CPER_ARM_ERR_CORRECTED_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) & CPER_ARM_ERR_CORRECTED_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (corrected)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) printk("%sthe error has been corrected\n", pfx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) printk("%sthe error has not been corrected\n", pfx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (error_info & CPER_ARM_ERR_VALID_PRECISE_PC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) precise_pc = ((error_info >> CPER_ARM_ERR_PRECISE_PC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) & CPER_ARM_ERR_PRECISE_PC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (precise_pc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) printk("%sPC is precise\n", pfx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) printk("%sPC is imprecise\n", pfx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (error_info & CPER_ARM_ERR_VALID_RESTARTABLE_PC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) restartable_pc = ((error_info >> CPER_ARM_ERR_RESTARTABLE_PC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) & CPER_ARM_ERR_RESTARTABLE_PC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (restartable_pc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) printk("%sProgram execution can be restarted reliably at the PC associated with the error.\n", pfx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* The rest of the fields are specific to bus errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (type != CPER_ARM_BUS_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (error_info & CPER_ARM_ERR_VALID_PARTICIPATION_TYPE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) participation_type = ((error_info >> CPER_ARM_ERR_PARTICIPATION_TYPE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) & CPER_ARM_ERR_PARTICIPATION_TYPE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (participation_type < ARRAY_SIZE(arm_bus_err_part_type_strs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) printk("%sparticipation type: %s\n", pfx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) arm_bus_err_part_type_strs[participation_type]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (error_info & CPER_ARM_ERR_VALID_TIME_OUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) time_out = ((error_info >> CPER_ARM_ERR_TIME_OUT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) & CPER_ARM_ERR_TIME_OUT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (time_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) printk("%srequest timed out\n", pfx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (error_info & CPER_ARM_ERR_VALID_ADDRESS_SPACE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) address_space = ((error_info >> CPER_ARM_ERR_ADDRESS_SPACE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) & CPER_ARM_ERR_ADDRESS_SPACE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (address_space < ARRAY_SIZE(arm_bus_err_addr_space_strs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) printk("%saddress space: %s\n", pfx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) arm_bus_err_addr_space_strs[address_space]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (error_info & CPER_ARM_ERR_VALID_MEM_ATTRIBUTES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) mem_attributes = ((error_info >> CPER_ARM_ERR_MEM_ATTRIBUTES_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) & CPER_ARM_ERR_MEM_ATTRIBUTES_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) printk("%smemory access attributes:0x%x\n", pfx, mem_attributes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (error_info & CPER_ARM_ERR_VALID_ACCESS_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) access_mode = ((error_info >> CPER_ARM_ERR_ACCESS_MODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) & CPER_ARM_ERR_ACCESS_MODE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (access_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) printk("%saccess mode: normal\n", pfx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) printk("%saccess mode: secure\n", pfx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) void cper_print_proc_arm(const char *pfx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) const struct cper_sec_proc_arm *proc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int i, len, max_ctx_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct cper_arm_err_info *err_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct cper_arm_ctx_info *ctx_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) char newpfx[64], infopfx[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) printk("%sMIDR: 0x%016llx\n", pfx, proc->midr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) len = proc->section_length - (sizeof(*proc) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) proc->err_info_num * (sizeof(*err_info)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (len < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) printk("%ssection length: %d\n", pfx, proc->section_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) printk("%ssection length is too small\n", pfx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) printk("%sfirmware-generated error record is incorrect\n", pfx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) printk("%sERR_INFO_NUM is %d\n", pfx, proc->err_info_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (proc->validation_bits & CPER_ARM_VALID_MPIDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) printk("%sMultiprocessor Affinity Register (MPIDR): 0x%016llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) pfx, proc->mpidr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (proc->validation_bits & CPER_ARM_VALID_AFFINITY_LEVEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) printk("%serror affinity level: %d\n", pfx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) proc->affinity_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (proc->validation_bits & CPER_ARM_VALID_RUNNING_STATE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) printk("%srunning state: 0x%x\n", pfx, proc->running_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) printk("%sPower State Coordination Interface state: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) pfx, proc->psci_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) snprintf(newpfx, sizeof(newpfx), "%s ", pfx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) err_info = (struct cper_arm_err_info *)(proc + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) for (i = 0; i < proc->err_info_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) printk("%sError info structure %d:\n", pfx, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) printk("%snum errors: %d\n", pfx, err_info->multiple_error + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (err_info->validation_bits & CPER_ARM_INFO_VALID_FLAGS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (err_info->flags & CPER_ARM_INFO_FLAGS_FIRST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) printk("%sfirst error captured\n", newpfx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (err_info->flags & CPER_ARM_INFO_FLAGS_LAST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) printk("%slast error captured\n", newpfx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (err_info->flags & CPER_ARM_INFO_FLAGS_PROPAGATED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) printk("%spropagated error captured\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) newpfx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (err_info->flags & CPER_ARM_INFO_FLAGS_OVERFLOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) printk("%soverflow occurred, error info is incomplete\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) newpfx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) printk("%serror_type: %d, %s\n", newpfx, err_info->type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) err_info->type < ARRAY_SIZE(cper_proc_error_type_strs) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) cper_proc_error_type_strs[err_info->type] : "unknown");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (err_info->validation_bits & CPER_ARM_INFO_VALID_ERR_INFO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) printk("%serror_info: 0x%016llx\n", newpfx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) err_info->error_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) snprintf(infopfx, sizeof(infopfx), "%s ", newpfx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) cper_print_arm_err_info(infopfx, err_info->type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) err_info->error_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (err_info->validation_bits & CPER_ARM_INFO_VALID_VIRT_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) printk("%svirtual fault address: 0x%016llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) newpfx, err_info->virt_fault_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (err_info->validation_bits & CPER_ARM_INFO_VALID_PHYSICAL_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) printk("%sphysical fault address: 0x%016llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) newpfx, err_info->physical_fault_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) err_info += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ctx_info = (struct cper_arm_ctx_info *)err_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) max_ctx_type = ARRAY_SIZE(arm_reg_ctx_strs) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) for (i = 0; i < proc->context_info_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) int size = sizeof(*ctx_info) + ctx_info->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) printk("%sContext info structure %d:\n", pfx, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (len < size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) printk("%ssection length is too small\n", newpfx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) printk("%sfirmware-generated error record is incorrect\n", pfx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (ctx_info->type > max_ctx_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) printk("%sInvalid context type: %d (max: %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) newpfx, ctx_info->type, max_ctx_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) printk("%sregister context type: %s\n", newpfx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) arm_reg_ctx_strs[ctx_info->type]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) print_hex_dump(newpfx, "", DUMP_PREFIX_OFFSET, 16, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) (ctx_info + 1), ctx_info->size, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) len -= size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ctx_info = (struct cper_arm_ctx_info *)((long)ctx_info + size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (len > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) printk("%sVendor specific error info has %u bytes:\n", pfx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) print_hex_dump(newpfx, "", DUMP_PREFIX_OFFSET, 16, 4, ctx_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) len, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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