^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _FIREWIRE_OHCI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _FIREWIRE_OHCI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /* OHCI register map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define OHCI1394_Version 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define OHCI1394_GUID_ROM 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define OHCI1394_ATRetries 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define OHCI1394_CSRData 0x00C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define OHCI1394_CSRCompareData 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define OHCI1394_CSRControl 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define OHCI1394_ConfigROMhdr 0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define OHCI1394_BusID 0x01C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define OHCI1394_BusOptions 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define OHCI1394_GUIDHi 0x024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define OHCI1394_GUIDLo 0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define OHCI1394_ConfigROMmap 0x034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define OHCI1394_PostedWriteAddressLo 0x038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define OHCI1394_PostedWriteAddressHi 0x03C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define OHCI1394_VendorID 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define OHCI1394_HCControlSet 0x050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define OHCI1394_HCControlClear 0x054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define OHCI1394_HCControl_BIBimageValid 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define OHCI1394_HCControl_noByteSwapData 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define OHCI1394_HCControl_programPhyEnable 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define OHCI1394_HCControl_aPhyEnhanceEnable 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define OHCI1394_HCControl_LPS 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define OHCI1394_HCControl_postedWriteEnable 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define OHCI1394_HCControl_linkEnable 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define OHCI1394_HCControl_softReset 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define OHCI1394_SelfIDBuffer 0x064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define OHCI1394_SelfIDCount 0x068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define OHCI1394_SelfIDCount_selfIDError 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OHCI1394_IRMultiChanMaskHiSet 0x070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define OHCI1394_IRMultiChanMaskHiClear 0x074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OHCI1394_IRMultiChanMaskLoSet 0x078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OHCI1394_IRMultiChanMaskLoClear 0x07C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OHCI1394_IntEventSet 0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define OHCI1394_IntEventClear 0x084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define OHCI1394_IntMaskSet 0x088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OHCI1394_IntMaskClear 0x08C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define OHCI1394_IsoXmitIntEventSet 0x090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OHCI1394_IsoXmitIntEventClear 0x094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OHCI1394_IsoXmitIntMaskSet 0x098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define OHCI1394_IsoXmitIntMaskClear 0x09C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define OHCI1394_IsoRecvIntEventSet 0x0A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OHCI1394_IsoRecvIntEventClear 0x0A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OHCI1394_IsoRecvIntMaskSet 0x0A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OHCI1394_IsoRecvIntMaskClear 0x0AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OHCI1394_InitialBandwidthAvailable 0x0B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OHCI1394_InitialChannelsAvailableHi 0x0B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OHCI1394_InitialChannelsAvailableLo 0x0B8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OHCI1394_FairnessControl 0x0DC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OHCI1394_LinkControlSet 0x0E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define OHCI1394_LinkControlClear 0x0E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OHCI1394_LinkControl_rcvSelfID (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OHCI1394_LinkControl_rcvPhyPkt (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OHCI1394_LinkControl_cycleTimerEnable (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define OHCI1394_LinkControl_cycleMaster (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define OHCI1394_LinkControl_cycleSource (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define OHCI1394_NodeID 0x0E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define OHCI1394_NodeID_idValid 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define OHCI1394_NodeID_root 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define OHCI1394_NodeID_nodeNumber 0x0000003f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define OHCI1394_NodeID_busNumber 0x0000ffc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define OHCI1394_PhyControl 0x0EC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define OHCI1394_PhyControl_Read(addr) (((addr) << 8) | 0x00008000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define OHCI1394_PhyControl_ReadDone 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define OHCI1394_PhyControl_ReadData(r) (((r) & 0x00ff0000) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define OHCI1394_PhyControl_Write(addr, data) (((addr) << 8) | (data) | 0x00004000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define OHCI1394_PhyControl_WritePending 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define OHCI1394_IsochronousCycleTimer 0x0F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define OHCI1394_AsReqFilterHiSet 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OHCI1394_AsReqFilterHiClear 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define OHCI1394_AsReqFilterLoSet 0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define OHCI1394_AsReqFilterLoClear 0x10C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define OHCI1394_PhyReqFilterHiSet 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define OHCI1394_PhyReqFilterHiClear 0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define OHCI1394_PhyReqFilterLoSet 0x118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define OHCI1394_PhyReqFilterLoClear 0x11C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define OHCI1394_PhyUpperBound 0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define OHCI1394_AsReqTrContextBase 0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define OHCI1394_AsReqTrContextControlSet 0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define OHCI1394_AsReqTrContextControlClear 0x184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define OHCI1394_AsReqTrCommandPtr 0x18C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define OHCI1394_AsRspTrContextBase 0x1A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define OHCI1394_AsRspTrContextControlSet 0x1A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define OHCI1394_AsRspTrContextControlClear 0x1A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define OHCI1394_AsRspTrCommandPtr 0x1AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define OHCI1394_AsReqRcvContextBase 0x1C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define OHCI1394_AsReqRcvContextControlSet 0x1C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define OHCI1394_AsReqRcvContextControlClear 0x1C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define OHCI1394_AsReqRcvCommandPtr 0x1CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define OHCI1394_AsRspRcvContextBase 0x1E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define OHCI1394_AsRspRcvContextControlSet 0x1E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define OHCI1394_AsRspRcvContextControlClear 0x1E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define OHCI1394_AsRspRcvCommandPtr 0x1EC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Isochronous transmit registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define OHCI1394_IsoXmitContextBase(n) (0x200 + 16 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define OHCI1394_IsoXmitContextControlSet(n) (0x200 + 16 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define OHCI1394_IsoXmitContextControlClear(n) (0x204 + 16 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define OHCI1394_IsoXmitCommandPtr(n) (0x20C + 16 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Isochronous receive registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define OHCI1394_IsoRcvContextBase(n) (0x400 + 32 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define OHCI1394_IsoRcvContextControlSet(n) (0x400 + 32 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define OHCI1394_IsoRcvContextControlClear(n) (0x404 + 32 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define OHCI1394_IsoRcvCommandPtr(n) (0x40C + 32 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define OHCI1394_IsoRcvContextMatch(n) (0x410 + 32 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Interrupts Mask/Events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define OHCI1394_reqTxComplete 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define OHCI1394_respTxComplete 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define OHCI1394_ARRQ 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define OHCI1394_ARRS 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define OHCI1394_RQPkt 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define OHCI1394_RSPkt 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define OHCI1394_isochTx 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define OHCI1394_isochRx 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define OHCI1394_postedWriteErr 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define OHCI1394_lockRespErr 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define OHCI1394_selfIDComplete 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define OHCI1394_busReset 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define OHCI1394_regAccessFail 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define OHCI1394_phy 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define OHCI1394_cycleSynch 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define OHCI1394_cycle64Seconds 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define OHCI1394_cycleLost 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define OHCI1394_cycleInconsistent 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define OHCI1394_unrecoverableError 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define OHCI1394_cycleTooLong 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define OHCI1394_phyRegRcvd 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define OHCI1394_masterIntEnable 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define OHCI1394_evt_no_status 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define OHCI1394_evt_long_packet 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define OHCI1394_evt_missing_ack 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define OHCI1394_evt_underrun 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define OHCI1394_evt_overrun 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define OHCI1394_evt_descriptor_read 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define OHCI1394_evt_data_read 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define OHCI1394_evt_data_write 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define OHCI1394_evt_bus_reset 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define OHCI1394_evt_timeout 0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define OHCI1394_evt_tcode_err 0xb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define OHCI1394_evt_reserved_b 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define OHCI1394_evt_reserved_c 0xd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define OHCI1394_evt_unknown 0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define OHCI1394_evt_flushed 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define OHCI1394_phy_tcode 0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #endif /* _FIREWIRE_OHCI_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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