Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Chip register definitions for PCILynx chipset.  Based on pcilynx.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * from the Linux 1394 drivers, but modified a bit so the names here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * match the specification exactly (even though they have weird names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * like xxx_OVER_FLOW, or arbitrary abbreviations like SNTRJ for "sent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * reject" etc.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define PCILYNX_MAX_REGISTER     0xfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define PCILYNX_MAX_MEMORY       0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define PCI_LATENCY_CACHELINE             0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define MISC_CONTROL                      0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define MISC_CONTROL_SWRESET              (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define SERIAL_EEPROM_CONTROL             0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define PCI_INT_STATUS                    0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define PCI_INT_ENABLE                    0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /* status and enable have identical bit numbers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define PCI_INT_INT_PEND                  (1<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define PCI_INT_FRC_INT                   (1<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define PCI_INT_SLV_ADR_PERR              (1<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define PCI_INT_SLV_DAT_PERR              (1<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define PCI_INT_MST_DAT_PERR              (1<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define PCI_INT_MST_DEV_TO                (1<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define PCI_INT_INT_SLV_TO                (1<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define PCI_INT_AUX_TO                    (1<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define PCI_INT_AUX_INT                   (1<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define PCI_INT_P1394_INT                 (1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define PCI_INT_DMA4_PCL                  (1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define PCI_INT_DMA4_HLT                  (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define PCI_INT_DMA3_PCL                  (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define PCI_INT_DMA3_HLT                  (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define PCI_INT_DMA2_PCL                  (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define PCI_INT_DMA2_HLT                  (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define PCI_INT_DMA1_PCL                  (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define PCI_INT_DMA1_HLT                  (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define PCI_INT_DMA0_PCL                  (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define PCI_INT_DMA0_HLT                  (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) /* all DMA interrupts combined: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define PCI_INT_DMA_ALL                   0x3ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define PCI_INT_DMA_HLT(chan)             (1 << (chan * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define PCI_INT_DMA_PCL(chan)             (1 << (chan * 2 + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define LBUS_ADDR                         0xb4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define LBUS_ADDR_SEL_RAM                 (0x0<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define LBUS_ADDR_SEL_ROM                 (0x1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define LBUS_ADDR_SEL_AUX                 (0x2<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define LBUS_ADDR_SEL_ZV                  (0x3<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define GPIO_CTRL_A                       0xb8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define GPIO_CTRL_B                       0xbc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define GPIO_DATA_BASE                    0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define DMA_BREG(base, chan)              (base + chan * 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define DMA_SREG(base, chan)              (base + chan * 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define PCL_NEXT_INVALID (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) /* transfer commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define PCL_CMD_RCV            (0x1<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define PCL_CMD_RCV_AND_UPDATE (0xa<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define PCL_CMD_XMT            (0x2<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define PCL_CMD_UNFXMT         (0xc<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define PCL_CMD_PCI_TO_LBUS    (0x8<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define PCL_CMD_LBUS_TO_PCI    (0x9<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) /* aux commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define PCL_CMD_NOP            (0x0<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define PCL_CMD_LOAD           (0x3<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define PCL_CMD_STOREQ         (0x4<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define PCL_CMD_STORED         (0xb<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define PCL_CMD_STORE0         (0x5<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define PCL_CMD_STORE1         (0x6<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define PCL_CMD_COMPARE        (0xe<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define PCL_CMD_SWAP_COMPARE   (0xf<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define PCL_CMD_ADD            (0xd<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define PCL_CMD_BRANCH         (0x7<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) /* BRANCH condition codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define PCL_COND_DMARDY_SET    (0x1<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define PCL_COND_DMARDY_CLEAR  (0x2<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define PCL_GEN_INTR           (1<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define PCL_LAST_BUFF          (1<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define PCL_LAST_CMD           (PCL_LAST_BUFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define PCL_WAITSTAT           (1<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define PCL_BIGENDIAN          (1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define PCL_ISOMODE            (1<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define DMA0_PREV_PCL                     0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define DMA1_PREV_PCL                     0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define DMA2_PREV_PCL                     0x140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define DMA3_PREV_PCL                     0x160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define DMA4_PREV_PCL                     0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define DMA_PREV_PCL(chan)                (DMA_BREG(DMA0_PREV_PCL, chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define DMA0_CURRENT_PCL                  0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DMA1_CURRENT_PCL                  0x124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define DMA2_CURRENT_PCL                  0x144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define DMA3_CURRENT_PCL                  0x164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define DMA4_CURRENT_PCL                  0x184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define DMA_CURRENT_PCL(chan)             (DMA_BREG(DMA0_CURRENT_PCL, chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define DMA0_CHAN_STAT                    0x10c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define DMA1_CHAN_STAT                    0x12c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define DMA2_CHAN_STAT                    0x14c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define DMA3_CHAN_STAT                    0x16c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define DMA4_CHAN_STAT                    0x18c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define DMA_CHAN_STAT(chan)               (DMA_BREG(DMA0_CHAN_STAT, chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* CHAN_STATUS registers share bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define DMA_CHAN_STAT_SELFID              (1<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define DMA_CHAN_STAT_ISOPKT              (1<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define DMA_CHAN_STAT_PCIERR              (1<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define DMA_CHAN_STAT_PKTERR              (1<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define DMA_CHAN_STAT_PKTCMPL             (1<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define DMA_CHAN_STAT_SPECIALACK          (1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define DMA0_CHAN_CTRL                    0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define DMA1_CHAN_CTRL                    0x130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define DMA2_CHAN_CTRL                    0x150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define DMA3_CHAN_CTRL                    0x170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define DMA4_CHAN_CTRL                    0x190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define DMA_CHAN_CTRL(chan)               (DMA_BREG(DMA0_CHAN_CTRL, chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* CHAN_CTRL registers share bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define DMA_CHAN_CTRL_ENABLE              (1<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define DMA_CHAN_CTRL_BUSY                (1<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define DMA_CHAN_CTRL_LINK                (1<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define DMA0_READY                        0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define DMA1_READY                        0x134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define DMA2_READY                        0x154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define DMA3_READY                        0x174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define DMA4_READY                        0x194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define DMA_READY(chan)                   (DMA_BREG(DMA0_READY, chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define DMA_GLOBAL_REGISTER               0x908
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define FIFO_SIZES                        0xa00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define FIFO_CONTROL                      0xa10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define FIFO_CONTROL_GRF_FLUSH            (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define FIFO_CONTROL_ITF_FLUSH            (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define FIFO_CONTROL_ATF_FLUSH            (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define FIFO_XMIT_THRESHOLD               0xa14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define DMA0_WORD0_CMP_VALUE              0xb00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define DMA1_WORD0_CMP_VALUE              0xb10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define DMA2_WORD0_CMP_VALUE              0xb20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define DMA3_WORD0_CMP_VALUE              0xb30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define DMA4_WORD0_CMP_VALUE              0xb40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define DMA_WORD0_CMP_VALUE(chan)	(DMA_SREG(DMA0_WORD0_CMP_VALUE, chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define DMA0_WORD0_CMP_ENABLE             0xb04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define DMA1_WORD0_CMP_ENABLE             0xb14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define DMA2_WORD0_CMP_ENABLE             0xb24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define DMA3_WORD0_CMP_ENABLE             0xb34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define DMA4_WORD0_CMP_ENABLE             0xb44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define DMA_WORD0_CMP_ENABLE(chan)	(DMA_SREG(DMA0_WORD0_CMP_ENABLE, chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define DMA0_WORD1_CMP_VALUE              0xb08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define DMA1_WORD1_CMP_VALUE              0xb18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define DMA2_WORD1_CMP_VALUE              0xb28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define DMA3_WORD1_CMP_VALUE              0xb38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define DMA4_WORD1_CMP_VALUE              0xb48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define DMA_WORD1_CMP_VALUE(chan)	(DMA_SREG(DMA0_WORD1_CMP_VALUE, chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define DMA0_WORD1_CMP_ENABLE             0xb0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define DMA1_WORD1_CMP_ENABLE             0xb1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define DMA2_WORD1_CMP_ENABLE             0xb2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define DMA3_WORD1_CMP_ENABLE             0xb3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define DMA4_WORD1_CMP_ENABLE             0xb4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define DMA_WORD1_CMP_ENABLE(chan)	(DMA_SREG(DMA0_WORD1_CMP_ENABLE, chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* word 1 compare enable flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define DMA_WORD1_CMP_MATCH_OTHERBUS      (1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define DMA_WORD1_CMP_MATCH_BROADCAST     (1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define DMA_WORD1_CMP_MATCH_BUS_BCAST     (1<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define DMA_WORD1_CMP_MATCH_LOCAL_NODE    (1<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define DMA_WORD1_CMP_MATCH_EXACT         (1<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define DMA_WORD1_CMP_ENABLE_SELF_ID      (1<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define DMA_WORD1_CMP_ENABLE_MASTER       (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define LINK_ID                           0xf00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define LINK_ID_BUS(id)                   (id<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define LINK_ID_NODE(id)                  (id<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define LINK_CONTROL                      0xf04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define LINK_CONTROL_BUSY                 (1<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define LINK_CONTROL_TX_ISO_EN            (1<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define LINK_CONTROL_RX_ISO_EN            (1<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define LINK_CONTROL_TX_ASYNC_EN          (1<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define LINK_CONTROL_RX_ASYNC_EN          (1<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define LINK_CONTROL_RESET_TX             (1<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define LINK_CONTROL_RESET_RX             (1<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define LINK_CONTROL_CYCMASTER            (1<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define LINK_CONTROL_CYCSOURCE            (1<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define LINK_CONTROL_CYCTIMEREN           (1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define LINK_CONTROL_RCV_CMP_VALID        (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define LINK_CONTROL_SNOOP_ENABLE         (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define CYCLE_TIMER                       0xf08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define LINK_PHY                          0xf0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define LINK_PHY_READ                     (1<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define LINK_PHY_WRITE                    (1<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define LINK_PHY_ADDR(addr)               (addr<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define LINK_PHY_WDATA(data)              (data<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define LINK_PHY_RADDR(addr)              (addr<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define LINK_INT_STATUS                   0xf14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define LINK_INT_ENABLE                   0xf18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* status and enable have identical bit numbers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define LINK_INT_LINK_INT                 (1<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define LINK_INT_PHY_TIME_OUT             (1<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define LINK_INT_PHY_REG_RCVD             (1<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define LINK_INT_PHY_BUSRESET             (1<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define LINK_INT_TX_RDY                   (1<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define LINK_INT_RX_DATA_RDY              (1<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define LINK_INT_IT_STUCK                 (1<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define LINK_INT_AT_STUCK                 (1<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define LINK_INT_SNTRJ                    (1<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define LINK_INT_HDR_ERR                  (1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define LINK_INT_TC_ERR                   (1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define LINK_INT_CYC_SEC                  (1<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define LINK_INT_CYC_STRT                 (1<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define LINK_INT_CYC_DONE                 (1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define LINK_INT_CYC_PEND                 (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define LINK_INT_CYC_LOST                 (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define LINK_INT_CYC_ARB_FAILED           (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define LINK_INT_GRF_OVER_FLOW            (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define LINK_INT_ITF_UNDER_FLOW           (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define LINK_INT_ATF_UNDER_FLOW           (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define LINK_INT_IARB_FAILED              (1<<0)