^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * init_ohci1394_dma.c - Initializes physical DMA on all OHCI 1394 controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2006-2007 Bernhard Kaindl <bk@suse.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Derived from drivers/ieee1394/ohci1394.c and arch/x86/kernel/early-quirks.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * this file has functions to:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * - scan the PCI very early on boot for all OHCI 1394-compliant controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * - reset and initialize them and make them join the IEEE1394 bus and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * - enable physical DMA on them to allow remote debugging
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * All code and data is marked as __init and __initdata, respective as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * during boot, all OHCI1394 controllers may be claimed by the firewire
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * stack and at this point, this code should not touch them anymore.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * To use physical DMA after the initialization of the firewire stack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * be sure that the stack enables it and (re-)attach after the bus reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * which may be caused by the firewire stack initialization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/pci.h> /* for PCI defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/pci-direct.h> /* for direct PCI config space access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/fixmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/init_ohci1394_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "ohci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) int __initdata init_ohci1394_dma_early;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct ohci {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) void __iomem *registers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static inline void reg_write(const struct ohci *ohci, int offset, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) writel(data, ohci->registers + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static inline u32 reg_read(const struct ohci *ohci, int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return readl(ohci->registers + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OHCI_LOOP_COUNT 100 /* Number of loops for reg read waits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* Reads a PHY register of an OHCI-1394 controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static inline u8 __init get_phy_reg(struct ohci *ohci, u8 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | 0x00008000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) for (i = 0; i < OHCI_LOOP_COUNT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (reg_read(ohci, OHCI1394_PhyControl) & 0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) r = reg_read(ohci, OHCI1394_PhyControl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return (r & 0x00ff0000) >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Writes to a PHY register of an OHCI-1394 controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static inline void __init set_phy_reg(struct ohci *ohci, u8 addr, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | data | 0x00004000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) for (i = 0; i < OHCI_LOOP_COUNT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (!(reg_read(ohci, OHCI1394_PhyControl) & 0x00004000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* Resets an OHCI-1394 controller (for sane state before initialization) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static inline void __init init_ohci1394_soft_reset(struct ohci *ohci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) for (i = 0; i < OHCI_LOOP_COUNT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (!(reg_read(ohci, OHCI1394_HCControlSet)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) & OHCI1394_HCControl_softReset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define OHCI1394_MAX_AT_REQ_RETRIES 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Basic OHCI-1394 register and port inititalization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static inline void __init init_ohci1394_initialize(struct ohci *ohci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 bus_options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int num_ports, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Put some defaults to these undefined bus options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) bus_options = reg_read(ohci, OHCI1394_BusOptions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) bus_options |= 0x60000000; /* Enable CMC and ISC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) bus_options &= ~0x00ff0000; /* XXX: Set cyc_clk_acc to zero for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) bus_options &= ~0x18000000; /* Disable PMC and BMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) reg_write(ohci, OHCI1394_BusOptions, bus_options);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Set the bus number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) reg_write(ohci, OHCI1394_NodeID, 0x0000ffc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Enable posted writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) reg_write(ohci, OHCI1394_HCControlSet,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) OHCI1394_HCControl_postedWriteEnable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Clear link control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) reg_write(ohci, OHCI1394_LinkControlClear, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* enable phys */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) reg_write(ohci, OHCI1394_LinkControlSet,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) OHCI1394_LinkControl_rcvPhyPkt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Don't accept phy packets into AR request context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) reg_write(ohci, OHCI1394_LinkControlClear, 0x00000400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Clear the Isochonouys interrupt masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Accept asynchronous transfer requests from all nodes for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* Specify asynchronous transfer retries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) reg_write(ohci, OHCI1394_ATRetries,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) OHCI1394_MAX_AT_REQ_RETRIES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) (OHCI1394_MAX_AT_RESP_RETRIES<<4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) (OHCI1394_MAX_PHYS_RESP_RETRIES<<8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* We don't want hardware swapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) reg_write(ohci, OHCI1394_HCControlClear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) OHCI1394_HCControl_noByteSwapData);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Enable link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_linkEnable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* If anything is connected to a port, make sure it is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) num_ports = get_phy_reg(ohci, 2) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) for (i = 0; i < num_ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) set_phy_reg(ohci, 7, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) status = get_phy_reg(ohci, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (status & 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) set_phy_reg(ohci, 8, status & ~1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * init_ohci1394_wait_for_busresets - wait until bus resets are completed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * OHCI1394 initialization itself and any device going on- or offline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * and any cable issue cause a IEEE1394 bus reset. The OHCI1394 spec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * specifies that physical DMA is disabled on each bus reset and it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * has to be enabled after each bus reset when needed. We resort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * to polling here because on early boot, we have no interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static inline void __init init_ohci1394_wait_for_busresets(struct ohci *ohci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) int i, events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) for (i = 0; i < 9; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) mdelay(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) events = reg_read(ohci, OHCI1394_IntEventSet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (events & OHCI1394_busReset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) reg_write(ohci, OHCI1394_IntEventClear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) OHCI1394_busReset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * init_ohci1394_enable_physical_dma - Enable physical DMA for remote debugging
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * This enables remote DMA access over IEEE1394 from every host for the low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * 4GB of address space. DMA accesses above 4GB are not available currently.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static inline void __init init_ohci1394_enable_physical_dma(struct ohci *ohci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) reg_write(ohci, OHCI1394_PhyUpperBound, 0xffff0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * init_ohci1394_reset_and_init_dma - init controller and enable DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * This initializes the given controller and enables physical DMA engine in it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static inline void __init init_ohci1394_reset_and_init_dma(struct ohci *ohci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* Start off with a soft reset, clears everything to a sane state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) init_ohci1394_soft_reset(ohci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* Accessing some registers without LPS enabled may cause lock up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_LPS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* Disable and clear interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) mdelay(50); /* Wait 50msec to make sure we have full link enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) init_ohci1394_initialize(ohci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * The initialization causes at least one IEEE1394 bus reset. Enabling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * physical DMA only works *after* *all* bus resets have calmed down:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) init_ohci1394_wait_for_busresets(ohci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* We had to wait and do this now if we want to debug early problems */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) init_ohci1394_enable_physical_dma(ohci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * init_ohci1394_controller - Map the registers of the controller and init DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * This maps the registers of the specified controller and initializes it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static inline void __init init_ohci1394_controller(int num, int slot, int func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) unsigned long ohci_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct ohci ohci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) printk(KERN_INFO "init_ohci1394_dma: initializing OHCI-1394"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) " at %02x:%02x.%x\n", num, slot, func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ohci_base = read_pci_config(num, slot, func, PCI_BASE_ADDRESS_0+(0<<2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) & PCI_BASE_ADDRESS_MEM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) set_fixmap_nocache(FIX_OHCI1394_BASE, ohci_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ohci.registers = (void __iomem *)fix_to_virt(FIX_OHCI1394_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) init_ohci1394_reset_and_init_dma(&ohci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * debug_init_ohci1394_dma - scan for OHCI1394 controllers and init DMA on them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * Scans the whole PCI space for OHCI1394 controllers and inits DMA on them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) void __init init_ohci1394_dma_on_all_controllers(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int num, slot, func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) u32 class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (!early_pci_allowed())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* Poor man's PCI discovery, the only thing we can do at early boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) for (num = 0; num < 32; num++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) for (slot = 0; slot < 32; slot++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) for (func = 0; func < 8; func++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) class = read_pci_config(num, slot, func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) PCI_CLASS_REVISION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (class == 0xffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) continue; /* No device at this func */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (class>>8 != PCI_CLASS_SERIAL_FIREWIRE_OHCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) continue; /* Not an OHCI-1394 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) init_ohci1394_controller(num, slot, func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) break; /* Assume one controller per device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) printk(KERN_INFO "init_ohci1394_dma: finished initializing OHCI DMA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * setup_init_ohci1394_early - enables early OHCI1394 DMA initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static int __init setup_ohci1394_dma(char *opt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (!strcmp(opt, "early"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) init_ohci1394_dma_early = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* passing ohci1394_dma=early on boot causes early OHCI1394 DMA initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) early_param("ohci1394_dma", setup_ohci1394_dma);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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