Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * sm5502.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2014 Samsung Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #ifndef __LINUX_EXTCON_SM5502_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define __LINUX_EXTCON_SM5502_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) enum sm5502_types {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 	TYPE_SM5502,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) /* SM5502 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) enum sm5502_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	SM5502_REG_DEVICE_ID = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	SM5502_REG_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	SM5502_REG_INT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	SM5502_REG_INT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	SM5502_REG_INTMASK1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	SM5502_REG_INTMASK2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	SM5502_REG_ADC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	SM5502_REG_TIMING_SET1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	SM5502_REG_TIMING_SET2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	SM5502_REG_DEV_TYPE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	SM5502_REG_DEV_TYPE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	SM5502_REG_BUTTON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	SM5502_REG_BUTTON2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	SM5502_REG_CAR_KIT_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	SM5502_REG_RSVD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	SM5502_REG_RSVD2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	SM5502_REG_RSVD3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	SM5502_REG_RSVD4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	SM5502_REG_MANUAL_SW1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	SM5502_REG_MANUAL_SW2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	SM5502_REG_DEV_TYPE3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	SM5502_REG_RSVD5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	SM5502_REG_RSVD6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	SM5502_REG_RSVD7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	SM5502_REG_RSVD8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	SM5502_REG_RSVD9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	SM5502_REG_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	SM5502_REG_RSVD10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	SM5502_REG_RESERVED_ID1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	SM5502_REG_RSVD11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	SM5502_REG_RSVD12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	SM5502_REG_RESERVED_ID2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	SM5502_REG_RSVD13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	SM5502_REG_OCP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	SM5502_REG_RSVD14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	SM5502_REG_RSVD15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	SM5502_REG_RSVD16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	SM5502_REG_RSVD17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	SM5502_REG_RSVD18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	SM5502_REG_RSVD19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	SM5502_REG_RSVD20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	SM5502_REG_RSVD21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	SM5502_REG_RSVD22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	SM5502_REG_RSVD23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	SM5502_REG_RSVD24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	SM5502_REG_RSVD25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	SM5502_REG_RSVD26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	SM5502_REG_RSVD27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	SM5502_REG_RSVD28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	SM5502_REG_RSVD29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	SM5502_REG_RSVD30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	SM5502_REG_RSVD31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	SM5502_REG_RSVD32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	SM5502_REG_RSVD33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	SM5502_REG_RSVD34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	SM5502_REG_RSVD35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	SM5502_REG_RSVD36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	SM5502_REG_RESERVED_ID3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	SM5502_REG_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) /* Define SM5502 MASK/SHIFT constant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define SM5502_REG_DEVICE_ID_VENDOR_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define SM5502_REG_DEVICE_ID_VERSION_SHIFT	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define SM5502_REG_DEVICE_ID_VENDOR_MASK	(0x3 << SM5502_REG_DEVICE_ID_VENDOR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define SM5502_REG_DEVICE_ID_VERSION_MASK	(0x1f << SM5502_REG_DEVICE_ID_VERSION_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define SM5502_REG_CONTROL_MASK_INT_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define SM5502_REG_CONTROL_WAIT_SHIFT		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define SM5502_REG_CONTROL_MANUAL_SW_SHIFT	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define SM5502_REG_CONTROL_RAW_DATA_SHIFT	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define SM5502_REG_CONTROL_SW_OPEN_SHIFT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define SM5502_REG_CONTROL_MASK_INT_MASK	(0x1 << SM5502_REG_CONTROL_MASK_INT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define SM5502_REG_CONTROL_WAIT_MASK		(0x1 << SM5502_REG_CONTROL_WAIT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define SM5502_REG_CONTROL_MANUAL_SW_MASK	(0x1 << SM5502_REG_CONTROL_MANUAL_SW_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define SM5502_REG_CONTROL_RAW_DATA_MASK	(0x1 << SM5502_REG_CONTROL_RAW_DATA_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define SM5502_REG_CONTROL_SW_OPEN_MASK		(0x1 << SM5502_REG_CONTROL_SW_OPEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define SM5502_REG_INTM1_ATTACH_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define SM5502_REG_INTM1_DETACH_SHIFT		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define SM5502_REG_INTM1_KP_SHIFT		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define SM5502_REG_INTM1_LKP_SHIFT		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SM5502_REG_INTM1_LKR_SHIFT		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SM5502_REG_INTM1_OVP_EVENT_SHIFT	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SM5502_REG_INTM1_OCP_EVENT_SHIFT	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SM5502_REG_INTM1_OVP_OCP_DIS_SHIFT	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SM5502_REG_INTM1_ATTACH_MASK		(0x1 << SM5502_REG_INTM1_ATTACH_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SM5502_REG_INTM1_DETACH_MASK		(0x1 << SM5502_REG_INTM1_DETACH_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SM5502_REG_INTM1_KP_MASK		(0x1 << SM5502_REG_INTM1_KP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SM5502_REG_INTM1_LKP_MASK		(0x1 << SM5502_REG_INTM1_LKP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SM5502_REG_INTM1_LKR_MASK		(0x1 << SM5502_REG_INTM1_LKR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SM5502_REG_INTM1_OVP_EVENT_MASK		(0x1 << SM5502_REG_INTM1_OVP_EVENT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SM5502_REG_INTM1_OCP_EVENT_MASK		(0x1 << SM5502_REG_INTM1_OCP_EVENT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SM5502_REG_INTM1_OVP_OCP_DIS_MASK	(0x1 << SM5502_REG_INTM1_OVP_OCP_DIS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SM5502_REG_INTM2_VBUS_DET_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SM5502_REG_INTM2_REV_ACCE_SHIFT		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SM5502_REG_INTM2_ADC_CHG_SHIFT		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SM5502_REG_INTM2_STUCK_KEY_SHIFT	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SM5502_REG_INTM2_STUCK_KEY_RCV_SHIFT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SM5502_REG_INTM2_MHL_SHIFT		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SM5502_REG_INTM2_VBUS_DET_MASK		(0x1 << SM5502_REG_INTM2_VBUS_DET_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SM5502_REG_INTM2_REV_ACCE_MASK		(0x1 << SM5502_REG_INTM2_REV_ACCE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SM5502_REG_INTM2_ADC_CHG_MASK		(0x1 << SM5502_REG_INTM2_ADC_CHG_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SM5502_REG_INTM2_STUCK_KEY_MASK		(0x1 << SM5502_REG_INTM2_STUCK_KEY_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SM5502_REG_INTM2_STUCK_KEY_RCV_MASK	(0x1 << SM5502_REG_INTM2_STUCK_KEY_RCV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SM5502_REG_INTM2_MHL_MASK		(0x1 << SM5502_REG_INTM2_MHL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SM5502_REG_ADC_SHIFT			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SM5502_REG_ADC_MASK			(0x1f << SM5502_REG_ADC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SM5502_REG_TIMING_SET1_KEY_PRESS_SHIFT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SM5502_REG_TIMING_SET1_KEY_PRESS_MASK	(0xf << SM5502_REG_TIMING_SET1_KEY_PRESS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define TIMING_KEY_PRESS_100MS			0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define TIMING_KEY_PRESS_200MS			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define TIMING_KEY_PRESS_300MS			0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define TIMING_KEY_PRESS_400MS			0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define TIMING_KEY_PRESS_500MS			0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define TIMING_KEY_PRESS_600MS			0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define TIMING_KEY_PRESS_700MS			0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define TIMING_KEY_PRESS_800MS			0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define TIMING_KEY_PRESS_900MS			0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define TIMING_KEY_PRESS_1000MS			0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SM5502_REG_TIMING_SET1_ADC_DET_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SM5502_REG_TIMING_SET1_ADC_DET_MASK	(0xf << SM5502_REG_TIMING_SET1_ADC_DET_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define TIMING_ADC_DET_50MS			0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define TIMING_ADC_DET_100MS			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define TIMING_ADC_DET_150MS			0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define TIMING_ADC_DET_200MS			0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define TIMING_ADC_DET_300MS			0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define TIMING_ADC_DET_400MS			0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define TIMING_ADC_DET_500MS			0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define TIMING_ADC_DET_600MS			0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define TIMING_ADC_DET_700MS			0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define TIMING_ADC_DET_800MS			0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define TIMING_ADC_DET_900MS			0xA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define TIMING_ADC_DET_1000MS			0xB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SM5502_REG_TIMING_SET2_SW_WAIT_SHIFT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SM5502_REG_TIMING_SET2_SW_WAIT_MASK	(0xf << SM5502_REG_TIMING_SET2_SW_WAIT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define TIMING_SW_WAIT_10MS			0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define TIMING_SW_WAIT_30MS			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define TIMING_SW_WAIT_50MS			0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define TIMING_SW_WAIT_70MS			0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define TIMING_SW_WAIT_90MS			0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define TIMING_SW_WAIT_110MS			0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define TIMING_SW_WAIT_130MS			0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define TIMING_SW_WAIT_150MS			0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define TIMING_SW_WAIT_170MS			0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define TIMING_SW_WAIT_190MS			0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define TIMING_SW_WAIT_210MS			0xA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SM5502_REG_TIMING_SET2_LONG_KEY_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define SM5502_REG_TIMING_SET2_LONG_KEY_MASK	(0xf << SM5502_REG_TIMING_SET2_LONG_KEY_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define TIMING_LONG_KEY_300MS			0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define TIMING_LONG_KEY_400MS			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define TIMING_LONG_KEY_500MS			0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define TIMING_LONG_KEY_600MS			0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define TIMING_LONG_KEY_700MS			0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define TIMING_LONG_KEY_800MS			0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define TIMING_LONG_KEY_900MS			0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define TIMING_LONG_KEY_1000MS			0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define TIMING_LONG_KEY_1100MS			0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define TIMING_LONG_KEY_1200MS			0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define TIMING_LONG_KEY_1300MS			0xA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define TIMING_LONG_KEY_1400MS			0xB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define TIMING_LONG_KEY_1500MS			0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define SM5502_REG_DEV_TYPE1_AUDIO_TYPE1_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define SM5502_REG_DEV_TYPE1_AUDIO_TYPE2_SHIFT		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define SM5502_REG_DEV_TYPE1_USB_SDP_SHIFT		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define SM5502_REG_DEV_TYPE1_UART_SHIFT			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define SM5502_REG_DEV_TYPE1_CAR_KIT_CHARGER_SHIFT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define SM5502_REG_DEV_TYPE1_USB_CHG_SHIFT		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define SM5502_REG_DEV_TYPE1_DEDICATED_CHG_SHIFT	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define SM5502_REG_DEV_TYPE1_USB_OTG_SHIFT		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define SM5502_REG_DEV_TYPE1_AUDIO_TYPE1_MASK		(0x1 << SM5502_REG_DEV_TYPE1_AUDIO_TYPE1_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define SM5502_REG_DEV_TYPE1_AUDIO_TYPE1__MASK		(0x1 << SM5502_REG_DEV_TYPE1_AUDIO_TYPE2_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define SM5502_REG_DEV_TYPE1_USB_SDP_MASK		(0x1 << SM5502_REG_DEV_TYPE1_USB_SDP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define SM5502_REG_DEV_TYPE1_UART_MASK			(0x1 << SM5502_REG_DEV_TYPE1_UART_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define SM5502_REG_DEV_TYPE1_CAR_KIT_CHARGER_MASK	(0x1 << SM5502_REG_DEV_TYPE1_CAR_KIT_CHARGER_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define SM5502_REG_DEV_TYPE1_USB_CHG_MASK		(0x1 << SM5502_REG_DEV_TYPE1_USB_CHG_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define SM5502_REG_DEV_TYPE1_DEDICATED_CHG_MASK		(0x1 << SM5502_REG_DEV_TYPE1_DEDICATED_CHG_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define SM5502_REG_DEV_TYPE1_USB_OTG_MASK		(0x1 << SM5502_REG_DEV_TYPE1_USB_OTG_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define SM5502_REG_DEV_TYPE2_JIG_USB_ON_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define SM5502_REG_DEV_TYPE2_JIG_USB_OFF_SHIFT		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define SM5502_REG_DEV_TYPE2_JIG_UART_ON_SHIFT		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define SM5502_REG_DEV_TYPE2_JIG_UART_OFF_SHIFT		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define SM5502_REG_DEV_TYPE2_PPD_SHIFT			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define SM5502_REG_DEV_TYPE2_TTY_SHIFT			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define SM5502_REG_DEV_TYPE2_AV_CABLE_SHIFT		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define SM5502_REG_DEV_TYPE2_JIG_USB_ON_MASK		(0x1 << SM5502_REG_DEV_TYPE2_JIG_USB_ON_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define SM5502_REG_DEV_TYPE2_JIG_USB_OFF_MASK		(0x1 << SM5502_REG_DEV_TYPE2_JIG_USB_OFF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define SM5502_REG_DEV_TYPE2_JIG_UART_ON_MASK		(0x1 << SM5502_REG_DEV_TYPE2_JIG_UART_ON_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define SM5502_REG_DEV_TYPE2_JIG_UART_OFF_MASK		(0x1 << SM5502_REG_DEV_TYPE2_JIG_UART_OFF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define SM5502_REG_DEV_TYPE2_PPD_MASK			(0x1 << SM5502_REG_DEV_TYPE2_PPD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define SM5502_REG_DEV_TYPE2_TTY_MASK			(0x1 << SM5502_REG_DEV_TYPE2_TTY_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define SM5502_REG_DEV_TYPE2_AV_CABLE_MASK		(0x1 << SM5502_REG_DEV_TYPE2_AV_CABLE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define SM5502_REG_MANUAL_SW1_VBUSIN_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define SM5502_REG_MANUAL_SW1_DP_SHIFT		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define SM5502_REG_MANUAL_SW1_DM_SHIFT		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define SM5502_REG_MANUAL_SW1_VBUSIN_MASK	(0x3 << SM5502_REG_MANUAL_SW1_VBUSIN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define SM5502_REG_MANUAL_SW1_DP_MASK		(0x7 << SM5502_REG_MANUAL_SW1_DP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define SM5502_REG_MANUAL_SW1_DM_MASK		(0x7 << SM5502_REG_MANUAL_SW1_DM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define VBUSIN_SWITCH_OPEN			0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define VBUSIN_SWITCH_VBUSOUT			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define VBUSIN_SWITCH_MIC			0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define VBUSIN_SWITCH_VBUSOUT_WITH_USB		0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define DM_DP_CON_SWITCH_OPEN			0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define DM_DP_CON_SWITCH_USB			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define DM_DP_CON_SWITCH_AUDIO			0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define DM_DP_CON_SWITCH_UART			0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define DM_DP_SWITCH_OPEN			((DM_DP_CON_SWITCH_OPEN <<SM5502_REG_MANUAL_SW1_DP_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 						| (DM_DP_CON_SWITCH_OPEN <<SM5502_REG_MANUAL_SW1_DM_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define DM_DP_SWITCH_USB			((DM_DP_CON_SWITCH_USB <<SM5502_REG_MANUAL_SW1_DP_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 						| (DM_DP_CON_SWITCH_USB <<SM5502_REG_MANUAL_SW1_DM_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define DM_DP_SWITCH_AUDIO			((DM_DP_CON_SWITCH_AUDIO <<SM5502_REG_MANUAL_SW1_DP_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 						| (DM_DP_CON_SWITCH_AUDIO <<SM5502_REG_MANUAL_SW1_DM_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define DM_DP_SWITCH_UART			((DM_DP_CON_SWITCH_UART <<SM5502_REG_MANUAL_SW1_DP_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 						| (DM_DP_CON_SWITCH_UART <<SM5502_REG_MANUAL_SW1_DM_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define SM5502_REG_RESET_MASK			(0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* SM5502 Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) enum sm5502_irq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	/* INT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	SM5502_IRQ_INT1_ATTACH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	SM5502_IRQ_INT1_DETACH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	SM5502_IRQ_INT1_KP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	SM5502_IRQ_INT1_LKP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	SM5502_IRQ_INT1_LKR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	SM5502_IRQ_INT1_OVP_EVENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	SM5502_IRQ_INT1_OCP_EVENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	SM5502_IRQ_INT1_OVP_OCP_DIS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	/* INT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	SM5502_IRQ_INT2_VBUS_DET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	SM5502_IRQ_INT2_REV_ACCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	SM5502_IRQ_INT2_ADC_CHG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	SM5502_IRQ_INT2_STUCK_KEY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	SM5502_IRQ_INT2_STUCK_KEY_RCV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	SM5502_IRQ_INT2_MHL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	SM5502_IRQ_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define SM5502_IRQ_INT1_ATTACH_MASK		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define SM5502_IRQ_INT1_DETACH_MASK		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define SM5502_IRQ_INT1_KP_MASK			BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define SM5502_IRQ_INT1_LKP_MASK		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define SM5502_IRQ_INT1_LKR_MASK		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define SM5502_IRQ_INT1_OVP_EVENT_MASK		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define SM5502_IRQ_INT1_OCP_EVENT_MASK		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define SM5502_IRQ_INT1_OVP_OCP_DIS_MASK	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define SM5502_IRQ_INT2_VBUS_DET_MASK		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define SM5502_IRQ_INT2_REV_ACCE_MASK		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define SM5502_IRQ_INT2_ADC_CHG_MASK		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define SM5502_IRQ_INT2_STUCK_KEY_MASK		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define SM5502_IRQ_INT2_STUCK_KEY_RCV_MASK	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define SM5502_IRQ_INT2_MHL_MASK		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #endif /*  __LINUX_EXTCON_SM5502_H */