^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * rt8973a.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2014 Samsung Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __LINUX_EXTCON_RT8973A_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __LINUX_EXTCON_RT8973A_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) enum rt8973a_types {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) TYPE_RT8973A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* RT8973A registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) enum rt8973A_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) RT8973A_REG_DEVICE_ID = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) RT8973A_REG_CONTROL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) RT8973A_REG_INT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) RT8973A_REG_INT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) RT8973A_REG_INTM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) RT8973A_REG_INTM2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) RT8973A_REG_ADC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) RT8973A_REG_RSVD_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) RT8973A_REG_RSVD_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) RT8973A_REG_DEV1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) RT8973A_REG_DEV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) RT8973A_REG_RSVD_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) RT8973A_REG_RSVD_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) RT8973A_REG_RSVD_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) RT8973A_REG_RSVD_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) RT8973A_REG_RSVD_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) RT8973A_REG_RSVD_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) RT8973A_REG_RSVD_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) RT8973A_REG_MANUAL_SW1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) RT8973A_REG_MANUAL_SW2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) RT8973A_REG_RSVD_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) RT8973A_REG_RSVD_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) RT8973A_REG_RSVD_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) RT8973A_REG_RSVD_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) RT8973A_REG_RSVD_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) RT8973A_REG_RSVD_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) RT8973A_REG_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) RT8973A_REG_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Define RT8973A MASK/SHIFT constant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RT8973A_REG_DEVICE_ID_VENDOR_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RT8973A_REG_DEVICE_ID_VERSION_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RT8973A_REG_DEVICE_ID_VENDOR_MASK (0x7 << RT8973A_REG_DEVICE_ID_VENDOR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RT8973A_REG_DEVICE_ID_VERSION_MASK (0x1f << RT8973A_REG_DEVICE_ID_VERSION_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RT8973A_REG_CONTROL1_INTM_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RT8973A_REG_CONTROL1_AUTO_CONFIG_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RT8973A_REG_CONTROL1_I2C_RST_EN_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RT8973A_REG_CONTROL1_SWITCH_OPEN_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RT8973A_REG_CONTROL1_CHGTYP_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RT8973A_REG_CONTROL1_USB_CHD_EN_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RT8973A_REG_CONTROL1_ADC_EN_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RT8973A_REG_CONTROL1_INTM_MASK (0x1 << RT8973A_REG_CONTROL1_INTM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RT8973A_REG_CONTROL1_AUTO_CONFIG_MASK (0x1 << RT8973A_REG_CONTROL1_AUTO_CONFIG_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RT8973A_REG_CONTROL1_I2C_RST_EN_MASK (0x1 << RT8973A_REG_CONTROL1_I2C_RST_EN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RT8973A_REG_CONTROL1_SWITCH_OPEN_MASK (0x1 << RT8973A_REG_CONTROL1_SWITCH_OPEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RT8973A_REG_CONTROL1_CHGTYP_MASK (0x1 << RT8973A_REG_CONTROL1_CHGTYP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define RT8973A_REG_CONTROL1_USB_CHD_EN_MASK (0x1 << RT8973A_REG_CONTROL1_USB_CHD_EN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define RT8973A_REG_CONTROL1_ADC_EN_MASK (0x1 << RT8973A_REG_CONTROL1_ADC_EN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define RT9873A_REG_INTM1_ATTACH_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define RT9873A_REG_INTM1_DETACH_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define RT9873A_REG_INTM1_CHGDET_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define RT9873A_REG_INTM1_DCD_T_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define RT9873A_REG_INTM1_OVP_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define RT9873A_REG_INTM1_CONNECT_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define RT9873A_REG_INTM1_ADC_CHG_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define RT9873A_REG_INTM1_OTP_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define RT9873A_REG_INTM1_ATTACH_MASK (0x1 << RT9873A_REG_INTM1_ATTACH_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define RT9873A_REG_INTM1_DETACH_MASK (0x1 << RT9873A_REG_INTM1_DETACH_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define RT9873A_REG_INTM1_CHGDET_MASK (0x1 << RT9873A_REG_INTM1_CHGDET_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define RT9873A_REG_INTM1_DCD_T_MASK (0x1 << RT9873A_REG_INTM1_DCD_T_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define RT9873A_REG_INTM1_OVP_MASK (0x1 << RT9873A_REG_INTM1_OVP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define RT9873A_REG_INTM1_CONNECT_MASK (0x1 << RT9873A_REG_INTM1_CONNECT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define RT9873A_REG_INTM1_ADC_CHG_MASK (0x1 << RT9873A_REG_INTM1_ADC_CHG_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define RT9873A_REG_INTM1_OTP_MASK (0x1 << RT9873A_REG_INTM1_OTP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define RT9873A_REG_INTM2_UVLO_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define RT9873A_REG_INTM2_POR_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define RT9873A_REG_INTM2_OTP_FET_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define RT9873A_REG_INTM2_OVP_FET_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define RT9873A_REG_INTM2_OCP_LATCH_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define RT9873A_REG_INTM2_OCP_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define RT9873A_REG_INTM2_OVP_OCP_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define RT9873A_REG_INTM2_UVLO_MASK (0x1 << RT9873A_REG_INTM2_UVLO_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define RT9873A_REG_INTM2_POR_MASK (0x1 << RT9873A_REG_INTM2_POR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define RT9873A_REG_INTM2_OTP_FET_MASK (0x1 << RT9873A_REG_INTM2_OTP_FET_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define RT9873A_REG_INTM2_OVP_FET_MASK (0x1 << RT9873A_REG_INTM2_OVP_FET_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define RT9873A_REG_INTM2_OCP_LATCH_MASK (0x1 << RT9873A_REG_INTM2_OCP_LATCH_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define RT9873A_REG_INTM2_OCP_MASK (0x1 << RT9873A_REG_INTM2_OCP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define RT9873A_REG_INTM2_OVP_OCP_MASK (0x1 << RT9873A_REG_INTM2_OVP_OCP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define RT8973A_REG_ADC_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define RT8973A_REG_ADC_MASK (0x1f << RT8973A_REG_ADC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define RT8973A_REG_DEV1_OTG_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define RT8973A_REG_DEV1_SDP_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define RT8973A_REG_DEV1_UART_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define RT8973A_REG_DEV1_CAR_KIT_TYPE1_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define RT8973A_REG_DEV1_CDPORT_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define RT8973A_REG_DEV1_DCPORT_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define RT8973A_REG_DEV1_OTG_MASK (0x1 << RT8973A_REG_DEV1_OTG_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define RT8973A_REG_DEV1_SDP_MASK (0x1 << RT8973A_REG_DEV1_SDP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define RT8973A_REG_DEV1_UART_MASK (0x1 << RT8973A_REG_DEV1_UART_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define RT8973A_REG_DEV1_CAR_KIT_TYPE1_MASK (0x1 << RT8973A_REG_DEV1_CAR_KIT_TYPE1_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define RT8973A_REG_DEV1_CDPORT_MASK (0x1 << RT8973A_REG_DEV1_CDPORT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define RT8973A_REG_DEV1_DCPORT_MASK (0x1 << RT8973A_REG_DEV1_DCPORT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define RT8973A_REG_DEV1_USB_MASK (RT8973A_REG_DEV1_SDP_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) | RT8973A_REG_DEV1_CDPORT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define RT8973A_REG_DEV2_JIG_USB_ON_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define RT8973A_REG_DEV2_JIG_USB_OFF_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define RT8973A_REG_DEV2_JIG_UART_ON_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define RT8973A_REG_DEV2_JIG_UART_OFF_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define RT8973A_REG_DEV2_JIG_USB_ON_MASK (0x1 << RT8973A_REG_DEV2_JIG_USB_ON_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define RT8973A_REG_DEV2_JIG_USB_OFF_MASK (0x1 << RT8973A_REG_DEV2_JIG_USB_OFF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define RT8973A_REG_DEV2_JIG_UART_ON_MASK (0x1 << RT8973A_REG_DEV2_JIG_UART_ON_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define RT8973A_REG_DEV2_JIG_UART_OFF_MASK (0x1 << RT8973A_REG_DEV2_JIG_UART_OFF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define RT8973A_REG_MANUAL_SW1_DP_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define RT8973A_REG_MANUAL_SW1_DM_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define RT8973A_REG_MANUAL_SW1_DP_MASK (0x7 << RT8973A_REG_MANUAL_SW1_DP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define RT8973A_REG_MANUAL_SW1_DM_MASK (0x7 << RT8973A_REG_MANUAL_SW1_DM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define DM_DP_CON_SWITCH_OPEN 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define DM_DP_CON_SWITCH_USB 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define DM_DP_CON_SWITCH_UART 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define DM_DP_SWITCH_OPEN ((DM_DP_CON_SWITCH_OPEN << RT8973A_REG_MANUAL_SW1_DP_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) | (DM_DP_CON_SWITCH_OPEN << RT8973A_REG_MANUAL_SW1_DM_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define DM_DP_SWITCH_USB ((DM_DP_CON_SWITCH_USB << RT8973A_REG_MANUAL_SW1_DP_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) | (DM_DP_CON_SWITCH_USB << RT8973A_REG_MANUAL_SW1_DM_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define DM_DP_SWITCH_UART ((DM_DP_CON_SWITCH_UART << RT8973A_REG_MANUAL_SW1_DP_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) | (DM_DP_CON_SWITCH_UART << RT8973A_REG_MANUAL_SW1_DM_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define RT8973A_REG_MANUAL_SW2_FET_ON_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define RT8973A_REG_MANUAL_SW2_JIG_ON_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define RT8973A_REG_MANUAL_SW2_BOOT_SW_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define RT8973A_REG_MANUAL_SW2_FET_ON_MASK (0x1 << RT8973A_REG_MANUAL_SW2_FET_ON_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define RT8973A_REG_MANUAL_SW2_JIG_ON_MASK (0x1 << RT8973A_REG_MANUAL_SW2_JIG_ON_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define RT8973A_REG_MANUAL_SW2_BOOT_SW_MASK (0x1 << RT8973A_REG_MANUAL_SW2_BOOT_SW_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define RT8973A_REG_MANUAL_SW2_FET_ON 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define RT8973A_REG_MANUAL_SW2_FET_OFF 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define RT8973A_REG_MANUAL_SW2_JIG_OFF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define RT8973A_REG_MANUAL_SW2_JIG_ON 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define RT8973A_REG_MANUAL_SW2_BOOT_SW_ON 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define RT8973A_REG_MANUAL_SW2_BOOT_SW_OFF 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define RT8973A_REG_RESET_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define RT8973A_REG_RESET_MASK (0x1 << RT8973A_REG_RESET_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define RT8973A_REG_RESET 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* RT8973A Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) enum rt8973a_irq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Interrupt1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) RT8973A_INT1_ATTACH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) RT8973A_INT1_DETACH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) RT8973A_INT1_CHGDET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) RT8973A_INT1_DCD_T,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) RT8973A_INT1_OVP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) RT8973A_INT1_CONNECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) RT8973A_INT1_ADC_CHG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) RT8973A_INT1_OTP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Interrupt2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) RT8973A_INT2_UVLO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) RT8973A_INT2_POR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) RT8973A_INT2_OTP_FET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) RT8973A_INT2_OVP_FET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) RT8973A_INT2_OCP_LATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) RT8973A_INT2_OCP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) RT8973A_INT2_OVP_OCP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) RT8973A_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define RT8973A_INT1_ATTACH_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define RT8973A_INT1_DETACH_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define RT8973A_INT1_CHGDET_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define RT8973A_INT1_DCD_T_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define RT8973A_INT1_OVP_MASK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define RT8973A_INT1_CONNECT_MASK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define RT8973A_INT1_ADC_CHG_MASK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define RT8973A_INT1_OTP_MASK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define RT8973A_INT2_UVLOT_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define RT8973A_INT2_POR_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define RT8973A_INT2_OTP_FET_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define RT8973A_INT2_OVP_FET_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define RT8973A_INT2_OCP_LATCH_MASK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define RT8973A_INT2_OCP_MASK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define RT8973A_INT2_OVP_OCP_MASK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #endif /* __LINUX_EXTCON_RT8973A_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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