Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Extcon charger detection driver for Intel Cherrytrail Whiskey Cove PMIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2017 Hans de Goede <hdegoede@redhat.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Based on various non upstream patches to support the CHT Whiskey Cove PMIC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2013-2015 Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/extcon-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/mfd/intel_soc_pmic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include "extcon-intel.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define CHT_WC_PHYCTRL			0x5e07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define CHT_WC_CHGRCTRL0		0x5e16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define CHT_WC_CHGRCTRL0_CHGRRESET	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define CHT_WC_CHGRCTRL0_EMRGCHREN	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define CHT_WC_CHGRCTRL0_EXTCHRDIS	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define CHT_WC_CHGRCTRL0_SWCONTROL	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define CHT_WC_CHGRCTRL0_TTLCK		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define CHT_WC_CHGRCTRL0_CCSM_OFF	BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define CHT_WC_CHGRCTRL0_DBPOFF		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define CHT_WC_CHGRCTRL0_CHR_WDT_NOKICK	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define CHT_WC_CHGRCTRL1			0x5e17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define CHT_WC_CHGRCTRL1_FUSB_INLMT_100		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define CHT_WC_CHGRCTRL1_FUSB_INLMT_150		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define CHT_WC_CHGRCTRL1_FUSB_INLMT_500		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define CHT_WC_CHGRCTRL1_FUSB_INLMT_900		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define CHT_WC_CHGRCTRL1_FUSB_INLMT_1500	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define CHT_WC_CHGRCTRL1_FTEMP_EVENT		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define CHT_WC_CHGRCTRL1_OTGMODE		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define CHT_WC_CHGRCTRL1_DBPEN			BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define CHT_WC_USBSRC			0x5e29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define CHT_WC_USBSRC_STS_MASK		GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define CHT_WC_USBSRC_STS_SUCCESS	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define CHT_WC_USBSRC_STS_FAIL		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define CHT_WC_USBSRC_TYPE_SHIFT	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define CHT_WC_USBSRC_TYPE_MASK		GENMASK(5, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define CHT_WC_USBSRC_TYPE_NONE		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define CHT_WC_USBSRC_TYPE_SDP		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define CHT_WC_USBSRC_TYPE_DCP		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define CHT_WC_USBSRC_TYPE_CDP		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define CHT_WC_USBSRC_TYPE_ACA		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define CHT_WC_USBSRC_TYPE_SE1		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define CHT_WC_USBSRC_TYPE_MHL		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define CHT_WC_USBSRC_TYPE_FLOATING	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define CHT_WC_USBSRC_TYPE_OTHER	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define CHT_WC_USBSRC_TYPE_DCP_EXTPHY	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define CHT_WC_CHGDISCTRL		0x5e2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define CHT_WC_CHGDISCTRL_OUT		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) /* 0 - open drain, 1 - regular push-pull output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define CHT_WC_CHGDISCTRL_DRV		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) /* 0 - pin is controlled by SW, 1 - by HW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define CHT_WC_CHGDISCTRL_FN		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define CHT_WC_PWRSRC_IRQ		0x6e03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define CHT_WC_PWRSRC_IRQ_MASK		0x6e0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define CHT_WC_PWRSRC_STS		0x6e1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define CHT_WC_PWRSRC_VBUS		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define CHT_WC_PWRSRC_DC		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define CHT_WC_PWRSRC_BATT		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define CHT_WC_PWRSRC_USBID_MASK	GENMASK(4, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define CHT_WC_PWRSRC_USBID_SHIFT	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define CHT_WC_PWRSRC_RID_ACA		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define CHT_WC_PWRSRC_RID_GND		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define CHT_WC_PWRSRC_RID_FLOAT		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define CHT_WC_VBUS_GPIO_CTLO		0x6e2d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define CHT_WC_VBUS_GPIO_CTLO_OUTPUT	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define CHT_WC_VBUS_GPIO_CTLO_DRV_OD	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define CHT_WC_VBUS_GPIO_CTLO_DIR_OUT	BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) enum cht_wc_mux_select {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	MUX_SEL_PMIC = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	MUX_SEL_SOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) static const unsigned int cht_wc_extcon_cables[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	EXTCON_USB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	EXTCON_USB_HOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	EXTCON_CHG_USB_SDP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	EXTCON_CHG_USB_CDP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	EXTCON_CHG_USB_DCP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	EXTCON_CHG_USB_ACA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	EXTCON_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct cht_wc_extcon_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	struct extcon_dev *edev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	unsigned int previous_cable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	bool usb_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int cht_wc_extcon_get_id(struct cht_wc_extcon_data *ext, int pwrsrc_sts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	switch ((pwrsrc_sts & CHT_WC_PWRSRC_USBID_MASK) >> CHT_WC_PWRSRC_USBID_SHIFT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	case CHT_WC_PWRSRC_RID_GND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		return INTEL_USB_ID_GND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	case CHT_WC_PWRSRC_RID_FLOAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		return INTEL_USB_ID_FLOAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	case CHT_WC_PWRSRC_RID_ACA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		 * Once we have IIO support for the GPADC we should read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		 * the USBID GPADC channel here and determine ACA role
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		 * based on that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		return INTEL_USB_ID_FLOAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int cht_wc_extcon_get_charger(struct cht_wc_extcon_data *ext,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 				     bool ignore_errors)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	int ret, usbsrc, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	/* Charger detection can take upto 600ms, wait 800ms max. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	timeout = jiffies + msecs_to_jiffies(800);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		ret = regmap_read(ext->regmap, CHT_WC_USBSRC, &usbsrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 			dev_err(ext->dev, "Error reading usbsrc: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		status = usbsrc & CHT_WC_USBSRC_STS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		if (status == CHT_WC_USBSRC_STS_SUCCESS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		    status == CHT_WC_USBSRC_STS_FAIL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		msleep(50); /* Wait a bit before retrying */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	} while (time_before(jiffies, timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	if (status != CHT_WC_USBSRC_STS_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		if (ignore_errors)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			return EXTCON_CHG_USB_SDP; /* Save fallback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		if (status == CHT_WC_USBSRC_STS_FAIL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 			dev_warn(ext->dev, "Could not detect charger type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 			dev_warn(ext->dev, "Timeout detecting charger type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		return EXTCON_CHG_USB_SDP; /* Save fallback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	usbsrc = (usbsrc & CHT_WC_USBSRC_TYPE_MASK) >> CHT_WC_USBSRC_TYPE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	switch (usbsrc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		dev_warn(ext->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			"Unhandled charger type %d, defaulting to SDP\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 			 ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		return EXTCON_CHG_USB_SDP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	case CHT_WC_USBSRC_TYPE_SDP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	case CHT_WC_USBSRC_TYPE_FLOATING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	case CHT_WC_USBSRC_TYPE_OTHER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		return EXTCON_CHG_USB_SDP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	case CHT_WC_USBSRC_TYPE_CDP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		return EXTCON_CHG_USB_CDP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	case CHT_WC_USBSRC_TYPE_DCP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	case CHT_WC_USBSRC_TYPE_DCP_EXTPHY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	case CHT_WC_USBSRC_TYPE_MHL: /* MHL2+ delivers upto 2A, treat as DCP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		return EXTCON_CHG_USB_DCP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	case CHT_WC_USBSRC_TYPE_ACA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		return EXTCON_CHG_USB_ACA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static void cht_wc_extcon_set_phymux(struct cht_wc_extcon_data *ext, u8 state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	ret = regmap_write(ext->regmap, CHT_WC_PHYCTRL, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		dev_err(ext->dev, "Error writing phyctrl: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static void cht_wc_extcon_set_5v_boost(struct cht_wc_extcon_data *ext,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 				       bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	int ret, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	 * The 5V boost converter is enabled through a gpio on the PMIC, since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	 * there currently is no gpio driver we access the gpio reg directly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	val = CHT_WC_VBUS_GPIO_CTLO_DRV_OD | CHT_WC_VBUS_GPIO_CTLO_DIR_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		val |= CHT_WC_VBUS_GPIO_CTLO_OUTPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	ret = regmap_write(ext->regmap, CHT_WC_VBUS_GPIO_CTLO, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		dev_err(ext->dev, "Error writing Vbus GPIO CTLO: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static void cht_wc_extcon_set_otgmode(struct cht_wc_extcon_data *ext,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 				      bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	unsigned int val = enable ? CHT_WC_CHGRCTRL1_OTGMODE : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	ret = regmap_update_bits(ext->regmap, CHT_WC_CHGRCTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 				 CHT_WC_CHGRCTRL1_OTGMODE, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		dev_err(ext->dev, "Error updating CHGRCTRL1 reg: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static void cht_wc_extcon_enable_charging(struct cht_wc_extcon_data *ext,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 					  bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	unsigned int val = enable ? 0 : CHT_WC_CHGDISCTRL_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	ret = regmap_update_bits(ext->regmap, CHT_WC_CHGDISCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 				 CHT_WC_CHGDISCTRL_OUT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		dev_err(ext->dev, "Error updating CHGDISCTRL reg: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* Small helper to sync EXTCON_CHG_USB_SDP and EXTCON_USB state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static void cht_wc_extcon_set_state(struct cht_wc_extcon_data *ext,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 				    unsigned int cable, bool state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	extcon_set_state_sync(ext->edev, cable, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	if (cable == EXTCON_CHG_USB_SDP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		extcon_set_state_sync(ext->edev, EXTCON_USB, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static void cht_wc_extcon_pwrsrc_event(struct cht_wc_extcon_data *ext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	int ret, pwrsrc_sts, id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	unsigned int cable = EXTCON_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	/* Ignore errors in host mode, as the 5v boost converter is on then */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	bool ignore_get_charger_errors = ext->usb_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	ret = regmap_read(ext->regmap, CHT_WC_PWRSRC_STS, &pwrsrc_sts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		dev_err(ext->dev, "Error reading pwrsrc status: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	id = cht_wc_extcon_get_id(ext, pwrsrc_sts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	if (id == INTEL_USB_ID_GND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		cht_wc_extcon_enable_charging(ext, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		cht_wc_extcon_set_otgmode(ext, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		/* The 5v boost causes a false VBUS / SDP detect, skip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		goto charger_det_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	cht_wc_extcon_set_otgmode(ext, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	cht_wc_extcon_enable_charging(ext, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	/* Plugged into a host/charger or not connected? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	if (!(pwrsrc_sts & CHT_WC_PWRSRC_VBUS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		/* Route D+ and D- to PMIC for future charger detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		cht_wc_extcon_set_phymux(ext, MUX_SEL_PMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		goto set_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	ret = cht_wc_extcon_get_charger(ext, ignore_get_charger_errors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		cable = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) charger_det_done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	/* Route D+ and D- to SoC for the host or gadget controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	cht_wc_extcon_set_phymux(ext, MUX_SEL_SOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) set_state:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	if (cable != ext->previous_cable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		cht_wc_extcon_set_state(ext, cable, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		cht_wc_extcon_set_state(ext, ext->previous_cable, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		ext->previous_cable = cable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	ext->usb_host = ((id == INTEL_USB_ID_GND) || (id == INTEL_USB_RID_A));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	extcon_set_state_sync(ext->edev, EXTCON_USB_HOST, ext->usb_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static irqreturn_t cht_wc_extcon_isr(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	struct cht_wc_extcon_data *ext = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	int ret, irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	ret = regmap_read(ext->regmap, CHT_WC_PWRSRC_IRQ, &irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		dev_err(ext->dev, "Error reading irqs: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	cht_wc_extcon_pwrsrc_event(ext);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	ret = regmap_write(ext->regmap, CHT_WC_PWRSRC_IRQ, irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		dev_err(ext->dev, "Error writing irqs: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static int cht_wc_extcon_sw_control(struct cht_wc_extcon_data *ext, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	int ret, mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	val = enable ? 0 : CHT_WC_CHGDISCTRL_FN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	ret = regmap_update_bits(ext->regmap, CHT_WC_CHGDISCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 				 CHT_WC_CHGDISCTRL_FN, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		dev_err(ext->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 			"Error setting sw control for CHGDIS pin: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 			ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	mask = CHT_WC_CHGRCTRL0_SWCONTROL | CHT_WC_CHGRCTRL0_CCSM_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	val = enable ? mask : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	ret = regmap_update_bits(ext->regmap, CHT_WC_CHGRCTRL0, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		dev_err(ext->dev, "Error setting sw control: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int cht_wc_extcon_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	struct intel_soc_pmic *pmic = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	struct cht_wc_extcon_data *ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	unsigned long mask = ~(CHT_WC_PWRSRC_VBUS | CHT_WC_PWRSRC_USBID_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	int pwrsrc_sts, id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	ext = devm_kzalloc(&pdev->dev, sizeof(*ext), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	if (!ext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	ext->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	ext->regmap = pmic->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	ext->previous_cable = EXTCON_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	/* Initialize extcon device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	ext->edev = devm_extcon_dev_allocate(ext->dev, cht_wc_extcon_cables);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	if (IS_ERR(ext->edev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		return PTR_ERR(ext->edev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	 * When a host-cable is detected the BIOS enables an external 5v boost
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	 * converter to power connected devices there are 2 problems with this:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	 * 1) This gets seen by the external battery charger as a valid Vbus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	 *    supply and it then tries to feed Vsys from this creating a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	 *    feedback loop which causes aprox. 300 mA extra battery drain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	 *    (and unless we drive the external-charger-disable pin high it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	 *    also tries to charge the battery causing even more feedback).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	 * 2) This gets seen by the pwrsrc block as a SDP USB Vbus supply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	 * Since the external battery charger has its own 5v boost converter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	 * which does not have these issues, we simply turn the separate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	 * external 5v boost converter off and leave it off entirely.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	cht_wc_extcon_set_5v_boost(ext, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	/* Enable sw control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	ret = cht_wc_extcon_sw_control(ext, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		goto disable_sw_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	/* Disable charging by external battery charger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	cht_wc_extcon_enable_charging(ext, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	/* Register extcon device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	ret = devm_extcon_dev_register(ext->dev, ext->edev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		dev_err(ext->dev, "Error registering extcon device: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		goto disable_sw_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	ret = regmap_read(ext->regmap, CHT_WC_PWRSRC_STS, &pwrsrc_sts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		dev_err(ext->dev, "Error reading pwrsrc status: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 		goto disable_sw_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	 * If no USB host or device connected, route D+ and D- to PMIC for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	 * initial charger detection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	id = cht_wc_extcon_get_id(ext, pwrsrc_sts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	if (id != INTEL_USB_ID_GND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 		cht_wc_extcon_set_phymux(ext, MUX_SEL_PMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	/* Get initial state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	cht_wc_extcon_pwrsrc_event(ext);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	ret = devm_request_threaded_irq(ext->dev, irq, NULL, cht_wc_extcon_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 					IRQF_ONESHOT, pdev->name, ext);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 		dev_err(ext->dev, "Error requesting interrupt: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 		goto disable_sw_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	/* Unmask irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	ret = regmap_write(ext->regmap, CHT_WC_PWRSRC_IRQ_MASK, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 		dev_err(ext->dev, "Error writing irq-mask: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 		goto disable_sw_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	platform_set_drvdata(pdev, ext);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) disable_sw_control:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	cht_wc_extcon_sw_control(ext, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static int cht_wc_extcon_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	struct cht_wc_extcon_data *ext = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	cht_wc_extcon_sw_control(ext, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static const struct platform_device_id cht_wc_extcon_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	{ .name = "cht_wcove_pwrsrc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) MODULE_DEVICE_TABLE(platform, cht_wc_extcon_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static struct platform_driver cht_wc_extcon_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	.probe = cht_wc_extcon_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	.remove = cht_wc_extcon_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	.id_table = cht_wc_extcon_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 		.name = "cht_wcove_pwrsrc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) module_platform_driver(cht_wc_extcon_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) MODULE_DESCRIPTION("Intel Cherrytrail Whiskey Cove PMIC extcon driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) MODULE_LICENSE("GPL v2");