^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * extcon-fsa9480.c - Fairchild Semiconductor FSA9480 extcon driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2019 Tomasz Figa <tomasz.figa@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Loosely based on old fsa9480 misc-device driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/kobject.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/extcon-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* FSA9480 I2C registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define FSA9480_REG_DEVID 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define FSA9480_REG_CTRL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define FSA9480_REG_INT1 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define FSA9480_REG_INT2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define FSA9480_REG_INT1_MASK 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define FSA9480_REG_INT2_MASK 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define FSA9480_REG_ADC 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define FSA9480_REG_TIMING1 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define FSA9480_REG_TIMING2 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define FSA9480_REG_DEV_T1 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define FSA9480_REG_DEV_T2 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define FSA9480_REG_BTN1 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define FSA9480_REG_BTN2 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define FSA9480_REG_CK 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define FSA9480_REG_CK_INT1 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define FSA9480_REG_CK_INT2 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define FSA9480_REG_CK_INTMASK1 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define FSA9480_REG_CK_INTMASK2 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define FSA9480_REG_MANSW1 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define FSA9480_REG_MANSW2 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define FSA9480_REG_END 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CON_SWITCH_OPEN (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CON_RAW_DATA (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CON_MANUAL_SW (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CON_WAIT (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CON_INT_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CON_MASK (CON_SWITCH_OPEN | CON_RAW_DATA | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) CON_MANUAL_SW | CON_WAIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Device Type 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DEV_USB_OTG 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DEV_DEDICATED_CHG 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DEV_USB_CHG 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DEV_CAR_KIT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DEV_UART 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DEV_USB 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DEV_AUDIO_2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DEV_AUDIO_1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DEV_T1_USB_MASK (DEV_USB_OTG | DEV_USB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DEV_T1_UART_MASK (DEV_UART)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DEV_T1_CHARGER_MASK (DEV_DEDICATED_CHG | DEV_USB_CHG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Device Type 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DEV_AV 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DEV_TTY 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DEV_PPD 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DEV_JIG_UART_OFF 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DEV_JIG_UART_ON 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define DEV_JIG_USB_OFF 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DEV_JIG_USB_ON 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define DEV_T2_USB_MASK (DEV_JIG_USB_OFF | DEV_JIG_USB_ON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DEV_T2_UART_MASK (DEV_JIG_UART_OFF | DEV_JIG_UART_ON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DEV_T2_JIG_MASK (DEV_JIG_USB_OFF | DEV_JIG_USB_ON | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) DEV_JIG_UART_OFF | DEV_JIG_UART_ON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * Manual Switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * D- [7:5] / D+ [4:2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * 000: Open all / 001: USB / 010: AUDIO / 011: UART / 100: V_AUDIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SW_VAUDIO ((4 << 5) | (4 << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SW_UART ((3 << 5) | (3 << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SW_AUDIO ((2 << 5) | (2 << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SW_DHOST ((1 << 5) | (1 << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SW_AUTO ((0 << 5) | (0 << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Interrupt 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define INT1_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define INT_DETACH (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define INT_ATTACH (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Interrupt 2 mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define INT2_MASK (0x1f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Timing Set 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define TIMING1_ADC_500MS (0x6 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct fsa9480_usbsw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct extcon_dev *edev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u16 cable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static const unsigned int fsa9480_extcon_cable[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) EXTCON_USB_HOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) EXTCON_USB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) EXTCON_CHG_USB_DCP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) EXTCON_CHG_USB_SDP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) EXTCON_CHG_USB_ACA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) EXTCON_JACK_LINE_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) EXTCON_JACK_VIDEO_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) EXTCON_JIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) EXTCON_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static const u64 cable_types[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) [DEV_USB_OTG] = BIT_ULL(EXTCON_USB_HOST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) [DEV_DEDICATED_CHG] = BIT_ULL(EXTCON_USB) | BIT_ULL(EXTCON_CHG_USB_DCP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) [DEV_USB_CHG] = BIT_ULL(EXTCON_USB) | BIT_ULL(EXTCON_CHG_USB_SDP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) [DEV_CAR_KIT] = BIT_ULL(EXTCON_USB) | BIT_ULL(EXTCON_CHG_USB_SDP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) | BIT_ULL(EXTCON_JACK_LINE_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) [DEV_UART] = BIT_ULL(EXTCON_JIG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) [DEV_USB] = BIT_ULL(EXTCON_USB) | BIT_ULL(EXTCON_CHG_USB_SDP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) [DEV_AUDIO_2] = BIT_ULL(EXTCON_JACK_LINE_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) [DEV_AUDIO_1] = BIT_ULL(EXTCON_JACK_LINE_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) [DEV_AV] = BIT_ULL(EXTCON_JACK_LINE_OUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) | BIT_ULL(EXTCON_JACK_VIDEO_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) [DEV_TTY] = BIT_ULL(EXTCON_JIG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) [DEV_PPD] = BIT_ULL(EXTCON_JACK_LINE_OUT) | BIT_ULL(EXTCON_CHG_USB_ACA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) [DEV_JIG_UART_OFF] = BIT_ULL(EXTCON_JIG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) [DEV_JIG_UART_ON] = BIT_ULL(EXTCON_JIG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) [DEV_JIG_USB_OFF] = BIT_ULL(EXTCON_USB) | BIT_ULL(EXTCON_JIG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) [DEV_JIG_USB_ON] = BIT_ULL(EXTCON_USB) | BIT_ULL(EXTCON_JIG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Define regmap configuration of FSA9480 for I2C communication */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static bool fsa9480_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) case FSA9480_REG_INT1_MASK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static const struct regmap_config fsa9480_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .volatile_reg = fsa9480_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .max_register = FSA9480_REG_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static int fsa9480_write_reg(struct fsa9480_usbsw *usbsw, int reg, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ret = regmap_write(usbsw->regmap, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) dev_err(usbsw->dev, "%s: err %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int fsa9480_read_reg(struct fsa9480_usbsw *usbsw, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) int ret, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ret = regmap_read(usbsw->regmap, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) dev_err(usbsw->dev, "%s: err %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int fsa9480_read_irq(struct fsa9480_usbsw *usbsw, int *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u8 regs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) ret = regmap_bulk_read(usbsw->regmap, FSA9480_REG_INT1, regs, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) dev_err(usbsw->dev, "%s: err %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) *value = regs[1] << 8 | regs[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static void fsa9480_handle_change(struct fsa9480_usbsw *usbsw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u16 mask, bool attached)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) while (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int dev = fls64(mask) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u64 cables = cable_types[dev];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) while (cables) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int cable = fls64(cables) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) extcon_set_state_sync(usbsw->edev, cable, attached);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) cables &= ~BIT_ULL(cable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) mask &= ~BIT_ULL(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static void fsa9480_detect_dev(struct fsa9480_usbsw *usbsw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) int val1, val2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) val1 = fsa9480_read_reg(usbsw, FSA9480_REG_DEV_T1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) val2 = fsa9480_read_reg(usbsw, FSA9480_REG_DEV_T2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (val1 < 0 || val2 < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) dev_err(usbsw->dev, "%s: failed to read registers", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) val = val2 << 8 | val1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) dev_info(usbsw->dev, "dev1: 0x%x, dev2: 0x%x\n", val1, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* handle detached cables first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) fsa9480_handle_change(usbsw, usbsw->cable & ~val, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* then handle attached ones */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) fsa9480_handle_change(usbsw, val & ~usbsw->cable, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) usbsw->cable = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static irqreturn_t fsa9480_irq_handler(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct fsa9480_usbsw *usbsw = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) int intr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* clear interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) fsa9480_read_irq(usbsw, &intr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (!intr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* device detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) fsa9480_detect_dev(usbsw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static int fsa9480_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct fsa9480_usbsw *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (!client->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) dev_err(&client->dev, "no interrupt provided\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) info->dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) i2c_set_clientdata(client, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* External connector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) info->edev = devm_extcon_dev_allocate(info->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) fsa9480_extcon_cable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (IS_ERR(info->edev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) dev_err(info->dev, "failed to allocate memory for extcon\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) ret = devm_extcon_dev_register(info->dev, info->edev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) dev_err(info->dev, "failed to register extcon device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) info->regmap = devm_regmap_init_i2c(client, &fsa9480_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (IS_ERR(info->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) ret = PTR_ERR(info->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) dev_err(info->dev, "failed to allocate register map: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* ADC Detect Time: 500ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) fsa9480_write_reg(info, FSA9480_REG_TIMING1, TIMING1_ADC_500MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* configure automatic switching */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) fsa9480_write_reg(info, FSA9480_REG_CTRL, CON_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* unmask interrupt (attach/detach only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) fsa9480_write_reg(info, FSA9480_REG_INT1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) INT1_MASK & ~(INT_ATTACH | INT_DETACH));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) fsa9480_write_reg(info, FSA9480_REG_INT2_MASK, INT2_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ret = devm_request_threaded_irq(info->dev, client->irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) fsa9480_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) "fsa9480", info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) dev_err(info->dev, "failed to request IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) device_init_wakeup(info->dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) fsa9480_detect_dev(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static int fsa9480_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static int fsa9480_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (device_may_wakeup(&client->dev) && client->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) enable_irq_wake(client->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static int fsa9480_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (device_may_wakeup(&client->dev) && client->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) disable_irq_wake(client->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static const struct dev_pm_ops fsa9480_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) SET_SYSTEM_SLEEP_PM_OPS(fsa9480_suspend, fsa9480_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static const struct i2c_device_id fsa9480_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) { "fsa9480", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) MODULE_DEVICE_TABLE(i2c, fsa9480_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static const struct of_device_id fsa9480_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) { .compatible = "fcs,fsa9480", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) { .compatible = "fcs,fsa880", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) MODULE_DEVICE_TABLE(of, fsa9480_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static struct i2c_driver fsa9480_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .name = "fsa9480",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .pm = &fsa9480_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .of_match_table = fsa9480_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .probe = fsa9480_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .remove = fsa9480_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .id_table = fsa9480_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static int __init fsa9480_module_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return i2c_add_driver(&fsa9480_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) subsys_initcall(fsa9480_module_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static void __exit fsa9480_module_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) i2c_del_driver(&fsa9480_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) module_exit(fsa9480_module_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) MODULE_DESCRIPTION("Fairchild Semiconductor FSA9480 extcon driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) MODULE_AUTHOR("Tomasz Figa <tomasz.figa@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags