^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Intel X38 Memory Controller kernel module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2008 Cluster Computing, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This file may be distributed under the terms of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * GNU General Public License.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This file is based on i3200_edac.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pci_ids.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/edac.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io-64-nonatomic-lo-hi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "edac_module.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define EDAC_MOD_STR "x38_edac"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PCI_DEVICE_ID_INTEL_X38_HB 0x29e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define X38_RANKS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define X38_RANKS_PER_CHANNEL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define X38_CHANNELS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* Intel X38 register addresses - device 0 function 0 - DRAM Controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define X38_MCHBAR_LOW 0x48 /* MCH Memory Mapped Register BAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define X38_MCHBAR_HIGH 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define X38_MCHBAR_MASK 0xfffffc000ULL /* bits 35:14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define X38_MMR_WINDOW_SIZE 16384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define X38_TOM 0xa0 /* Top of Memory (16b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * 15:10 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * 9:0 total populated physical memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define X38_TOM_MASK 0x3ff /* bits 9:0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define X38_TOM_SHIFT 26 /* 64MiB grain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define X38_ERRSTS 0xc8 /* Error Status Register (16b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * 15 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * 14 Isochronous TBWRR Run Behind FIFO Full
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * (ITCV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * 13 Isochronous TBWRR Run Behind FIFO Put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * (ITSTV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * 12 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * 11 MCH Thermal Sensor Event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * for SMI/SCI/SERR (GTSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * 10 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * 9 LOCK to non-DRAM Memory Flag (LCKF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * 8 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * 7 DRAM Throttle Flag (DTF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * 6:2 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * 1 Multi-bit DRAM ECC Error Flag (DMERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * 0 Single-bit DRAM ECC Error Flag (DSERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define X38_ERRSTS_UE 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define X38_ERRSTS_CE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define X38_ERRSTS_BITS (X38_ERRSTS_UE | X38_ERRSTS_CE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* Intel MMIO register space - device 0 function 0 - MMR space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define X38_C0DRB 0x200 /* Channel 0 DRAM Rank Boundary (16b x 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * 15:10 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * 9:0 Channel 0 DRAM Rank Boundary Address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define X38_C1DRB 0x600 /* Channel 1 DRAM Rank Boundary (16b x 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define X38_DRB_MASK 0x3ff /* bits 9:0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define X38_DRB_SHIFT 26 /* 64MiB grain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define X38_C0ECCERRLOG 0x280 /* Channel 0 ECC Error Log (64b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * 63:48 Error Column Address (ERRCOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * 47:32 Error Row Address (ERRROW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * 31:29 Error Bank Address (ERRBANK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * 28:27 Error Rank Address (ERRRANK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * 26:24 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * 23:16 Error Syndrome (ERRSYND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * 15: 2 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * 1 Multiple Bit Error Status (MERRSTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * 0 Correctable Error Status (CERRSTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define X38_C1ECCERRLOG 0x680 /* Channel 1 ECC Error Log (64b) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define X38_ECCERRLOG_CE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define X38_ECCERRLOG_UE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define X38_ECCERRLOG_RANK_BITS 0x18000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define X38_ECCERRLOG_SYNDROME_BITS 0xff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define X38_CAPID0 0xe0 /* see P.94 of spec for details */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static int x38_channel_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static int how_many_channel(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned char capid0_8b; /* 8th byte of CAPID0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) pci_read_config_byte(pdev, X38_CAPID0 + 8, &capid0_8b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (capid0_8b & 0x20) { /* check DCD: Dual Channel Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) edac_dbg(0, "In single channel mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) x38_channel_num = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) edac_dbg(0, "In dual channel mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) x38_channel_num = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return x38_channel_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static unsigned long eccerrlog_syndrome(u64 log)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return (log & X38_ECCERRLOG_SYNDROME_BITS) >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int eccerrlog_row(int channel, u64 log)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return ((log & X38_ECCERRLOG_RANK_BITS) >> 27) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) (channel * X38_RANKS_PER_CHANNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) enum x38_chips {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) X38 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct x38_dev_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) const char *ctl_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct x38_error_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u16 errsts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u16 errsts2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u64 eccerrlog[X38_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static const struct x38_dev_info x38_devs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) [X38] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .ctl_name = "x38"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static struct pci_dev *mci_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static int x38_registered = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static void x38_clear_error_info(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) pdev = to_pci_dev(mci->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * Clear any error bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * (Yes, we really clear bits by writing 1 to them.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) pci_write_bits16(pdev, X38_ERRSTS, X38_ERRSTS_BITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) X38_ERRSTS_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static void x38_get_and_clear_error_info(struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct x38_error_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) void __iomem *window = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) pdev = to_pci_dev(mci->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * This is a mess because there is no atomic way to read all the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * registers at once and the registers can transition from CE being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * overwritten by UE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) pci_read_config_word(pdev, X38_ERRSTS, &info->errsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (!(info->errsts & X38_ERRSTS_BITS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) info->eccerrlog[0] = lo_hi_readq(window + X38_C0ECCERRLOG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (x38_channel_num == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) info->eccerrlog[1] = lo_hi_readq(window + X38_C1ECCERRLOG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) pci_read_config_word(pdev, X38_ERRSTS, &info->errsts2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * If the error is the same for both reads then the first set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * of reads is valid. If there is a change then there is a CE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * with no info and the second set of reads is valid and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * should be UE info.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if ((info->errsts ^ info->errsts2) & X38_ERRSTS_BITS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) info->eccerrlog[0] = lo_hi_readq(window + X38_C0ECCERRLOG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (x38_channel_num == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) info->eccerrlog[1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) lo_hi_readq(window + X38_C1ECCERRLOG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) x38_clear_error_info(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static void x38_process_error_info(struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct x38_error_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u64 log;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (!(info->errsts & X38_ERRSTS_BITS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if ((info->errsts ^ info->errsts2) & X38_ERRSTS_BITS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) -1, -1, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) "UE overwrote CE", "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) info->errsts = info->errsts2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) for (channel = 0; channel < x38_channel_num; channel++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) log = info->eccerrlog[channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (log & X38_ECCERRLOG_UE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) eccerrlog_row(channel, log),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) -1, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) "x38 UE", "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) } else if (log & X38_ECCERRLOG_CE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 0, 0, eccerrlog_syndrome(log),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) eccerrlog_row(channel, log),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) -1, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) "x38 CE", "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static void x38_check(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct x38_error_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) edac_dbg(1, "MC%d\n", mci->mc_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) x38_get_and_clear_error_info(mci, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) x38_process_error_info(mci, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static void __iomem *x38_map_mchbar(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u64 mchbar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u32 mchbar_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u32 mchbar_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) void __iomem *window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) pci_read_config_dword(pdev, X38_MCHBAR_LOW, &u.mchbar_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) pci_write_config_dword(pdev, X38_MCHBAR_LOW, u.mchbar_low | 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) pci_read_config_dword(pdev, X38_MCHBAR_HIGH, &u.mchbar_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) u.mchbar &= X38_MCHBAR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (u.mchbar != (resource_size_t)u.mchbar) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) printk(KERN_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) "x38: mmio space beyond accessible range (0x%llx)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) (unsigned long long)u.mchbar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) window = ioremap(u.mchbar, X38_MMR_WINDOW_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (!window)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) printk(KERN_ERR "x38: cannot map mmio space at 0x%llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) (unsigned long long)u.mchbar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static void x38_get_drbs(void __iomem *window,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u16 drbs[X38_CHANNELS][X38_RANKS_PER_CHANNEL])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) for (i = 0; i < X38_RANKS_PER_CHANNEL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) drbs[0][i] = readw(window + X38_C0DRB + 2*i) & X38_DRB_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) drbs[1][i] = readw(window + X38_C1DRB + 2*i) & X38_DRB_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static bool x38_is_stacked(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u16 drbs[X38_CHANNELS][X38_RANKS_PER_CHANNEL])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) u16 tom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) pci_read_config_word(pdev, X38_TOM, &tom);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) tom &= X38_TOM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return drbs[X38_CHANNELS - 1][X38_RANKS_PER_CHANNEL - 1] == tom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static unsigned long drb_to_nr_pages(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u16 drbs[X38_CHANNELS][X38_RANKS_PER_CHANNEL],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) bool stacked, int channel, int rank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) n = drbs[channel][rank];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (rank > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) n -= drbs[channel][rank - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (stacked && (channel == 1) && drbs[channel][rank] ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) drbs[channel][X38_RANKS_PER_CHANNEL - 1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) n -= drbs[0][X38_RANKS_PER_CHANNEL - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) n <<= (X38_DRB_SHIFT - PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int x38_probe1(struct pci_dev *pdev, int dev_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct mem_ctl_info *mci = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct edac_mc_layer layers[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u16 drbs[X38_CHANNELS][X38_RANKS_PER_CHANNEL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) bool stacked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) void __iomem *window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) edac_dbg(0, "MC:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) window = x38_map_mchbar(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (!window)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) x38_get_drbs(window, drbs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) how_many_channel(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* FIXME: unconventional pvt_info usage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) layers[0].size = X38_RANKS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) layers[0].is_virt_csrow = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) layers[1].type = EDAC_MC_LAYER_CHANNEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) layers[1].size = x38_channel_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) layers[1].is_virt_csrow = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (!mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) edac_dbg(3, "MC: init mci\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) mci->pdev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) mci->mtype_cap = MEM_FLAG_DDR2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) mci->edac_ctl_cap = EDAC_FLAG_SECDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) mci->edac_cap = EDAC_FLAG_SECDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) mci->mod_name = EDAC_MOD_STR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) mci->ctl_name = x38_devs[dev_idx].ctl_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) mci->dev_name = pci_name(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) mci->edac_check = x38_check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) mci->ctl_page_to_phys = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) mci->pvt_info = window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) stacked = x38_is_stacked(pdev, drbs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * The dram rank boundary (DRB) reg values are boundary addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * for each DRAM rank with a granularity of 64MB. DRB regs are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * cumulative; the last one will contain the total memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * contained in all ranks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) for (i = 0; i < mci->nr_csrows; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) unsigned long nr_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct csrow_info *csrow = mci->csrows[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) nr_pages = drb_to_nr_pages(drbs, stacked,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) i / X38_RANKS_PER_CHANNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) i % X38_RANKS_PER_CHANNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (nr_pages == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) for (j = 0; j < x38_channel_num; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct dimm_info *dimm = csrow->channels[j]->dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) dimm->nr_pages = nr_pages / x38_channel_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) dimm->grain = nr_pages << PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) dimm->mtype = MEM_DDR2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) dimm->dtype = DEV_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) dimm->edac_mode = EDAC_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) x38_clear_error_info(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (edac_mc_add_mc(mci)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) edac_dbg(3, "MC: failed edac_mc_add_mc()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* get this far and it's successful */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) edac_dbg(3, "MC: success\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) iounmap(window);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static int x38_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) edac_dbg(0, "MC:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (pci_enable_device(pdev) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) rc = x38_probe1(pdev, ent->driver_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (!mci_pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) mci_pdev = pci_dev_get(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static void x38_remove_one(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct mem_ctl_info *mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) edac_dbg(0, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) mci = edac_mc_del_mc(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (!mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) iounmap(mci->pvt_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static const struct pci_device_id x38_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) PCI_VEND_DEV(INTEL, X38_HB), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) X38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) } /* 0 terminated list. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) MODULE_DEVICE_TABLE(pci, x38_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static struct pci_driver x38_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .name = EDAC_MOD_STR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .probe = x38_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .remove = x38_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .id_table = x38_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static int __init x38_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) int pci_rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) edac_dbg(3, "MC:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /* Ensure that the OPSTATE is set correctly for POLL or NMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) opstate_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) pci_rc = pci_register_driver(&x38_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (pci_rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) goto fail0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (!mci_pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) x38_registered = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) PCI_DEVICE_ID_INTEL_X38_HB, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (!mci_pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) edac_dbg(0, "x38 pci_get_device fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) pci_rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) goto fail1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) pci_rc = x38_init_one(mci_pdev, x38_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (pci_rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) edac_dbg(0, "x38 init fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) pci_rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) goto fail1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) fail1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) pci_unregister_driver(&x38_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) fail0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) pci_dev_put(mci_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return pci_rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static void __exit x38_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) edac_dbg(3, "MC:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) pci_unregister_driver(&x38_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (!x38_registered) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) x38_remove_one(mci_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) pci_dev_put(mci_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) module_init(x38_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) module_exit(x38_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) MODULE_AUTHOR("Cluster Computing, Inc. Hitoshi Mitake");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) MODULE_DESCRIPTION("MC support for Intel X38 memory hub controllers");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) module_param(edac_op_state, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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