Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Texas Instruments DDR3 ECC error correction and detection driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * This program is free software; you can redistribute it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * under the terms and conditions of the GNU General Public License,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * version 2, as published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * This program is distributed in the hope it will be useful, but WITHOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * You should have received a copy of the GNU General Public License along with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * this program.  If not, see <http://www.gnu.org/licenses/>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/edac.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include "edac_module.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) /* EMIF controller registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define EMIF_SDRAM_CONFIG		0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define EMIF_IRQ_STATUS			0x0ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define EMIF_IRQ_ENABLE_SET		0x0b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define EMIF_ECC_CTRL			0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define EMIF_1B_ECC_ERR_CNT		0x130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define EMIF_1B_ECC_ERR_THRSH		0x134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define EMIF_1B_ECC_ERR_ADDR_LOG	0x13c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define EMIF_2B_ECC_ERR_ADDR_LOG	0x140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /* Bit definitions for EMIF_SDRAM_CONFIG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define SDRAM_TYPE_SHIFT		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define SDRAM_TYPE_MASK			GENMASK(31, 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define SDRAM_TYPE_DDR3			(3 << SDRAM_TYPE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define SDRAM_TYPE_DDR2			(2 << SDRAM_TYPE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define SDRAM_NARROW_MODE_MASK		GENMASK(15, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define SDRAM_K2_NARROW_MODE_SHIFT	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define SDRAM_K2_NARROW_MODE_MASK	GENMASK(13, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define SDRAM_ROWSIZE_SHIFT		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define SDRAM_ROWSIZE_MASK		GENMASK(9, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define SDRAM_IBANK_SHIFT		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define SDRAM_IBANK_MASK		GENMASK(6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define SDRAM_K2_IBANK_SHIFT		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define SDRAM_K2_IBANK_MASK		GENMASK(6, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define SDRAM_K2_EBANK_SHIFT		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define SDRAM_K2_EBANK_MASK		BIT(SDRAM_K2_EBANK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define SDRAM_PAGESIZE_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define SDRAM_PAGESIZE_MASK		GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define SDRAM_K2_PAGESIZE_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define SDRAM_K2_PAGESIZE_MASK		GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define EMIF_1B_ECC_ERR_THRSH_SHIFT	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) /* IRQ bit definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define EMIF_1B_ECC_ERR			BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define EMIF_2B_ECC_ERR			BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define EMIF_WR_ECC_ERR			BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define EMIF_SYS_ERR			BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) /* Bit 31 enables ECC and 28 enables RMW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define ECC_ENABLED			(BIT(31) | BIT(28))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define EDAC_MOD_NAME			"ti-emif-edac"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	EMIF_TYPE_DRA7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	EMIF_TYPE_K2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) struct ti_edac {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) static u32 ti_edac_readl(struct ti_edac *edac, u16 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	return readl_relaxed(edac->reg + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) static void ti_edac_writel(struct ti_edac *edac, u32 val, u16 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	writel_relaxed(val, edac->reg + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static irqreturn_t ti_edac_isr(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	struct mem_ctl_info *mci = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	struct ti_edac *edac = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	u32 irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	u32 err_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	int err_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	irq_status = ti_edac_readl(edac, EMIF_IRQ_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	if (irq_status & EMIF_1B_ECC_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		err_addr = ti_edac_readl(edac, EMIF_1B_ECC_ERR_ADDR_LOG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		err_count = ti_edac_readl(edac, EMIF_1B_ECC_ERR_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		ti_edac_writel(edac, err_count, EMIF_1B_ECC_ERR_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 				     err_addr >> PAGE_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 				     err_addr & ~PAGE_MASK, -1, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 				     mci->ctl_name, "1B");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	if (irq_status & EMIF_2B_ECC_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		err_addr = ti_edac_readl(edac, EMIF_2B_ECC_ERR_ADDR_LOG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 				     err_addr >> PAGE_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 				     err_addr & ~PAGE_MASK, -1, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 				     mci->ctl_name, "2B");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	if (irq_status & EMIF_WR_ECC_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 				     0, 0, -1, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 				     mci->ctl_name, "WR");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	ti_edac_writel(edac, irq_status, EMIF_IRQ_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static void ti_edac_setup_dimm(struct mem_ctl_info *mci, u32 type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	struct dimm_info *dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	struct ti_edac *edac = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	int bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	u32 memsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	dimm = edac_get_dimm(mci, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	val = ti_edac_readl(edac, EMIF_SDRAM_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	if (type == EMIF_TYPE_DRA7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		bits = ((val & SDRAM_PAGESIZE_MASK) >> SDRAM_PAGESIZE_SHIFT) + 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		bits += ((val & SDRAM_ROWSIZE_MASK) >> SDRAM_ROWSIZE_SHIFT) + 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		bits += (val & SDRAM_IBANK_MASK) >> SDRAM_IBANK_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		if (val & SDRAM_NARROW_MODE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			bits++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 			dimm->dtype = DEV_X16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			bits += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 			dimm->dtype = DEV_X32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		bits = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		bits += ((val & SDRAM_K2_PAGESIZE_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 			SDRAM_K2_PAGESIZE_SHIFT) + 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		bits += (val & SDRAM_K2_IBANK_MASK) >> SDRAM_K2_IBANK_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		bits += (val & SDRAM_K2_EBANK_MASK) >> SDRAM_K2_EBANK_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		val = (val & SDRAM_K2_NARROW_MODE_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 			SDRAM_K2_NARROW_MODE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 			bits += 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			dimm->dtype = DEV_X64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 			bits += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			dimm->dtype = DEV_X32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 			bits++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 			dimm->dtype = DEV_X16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	memsize = 1 << bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	dimm->nr_pages = memsize >> PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	dimm->grain = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	if ((val & SDRAM_TYPE_MASK) == SDRAM_TYPE_DDR2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		dimm->mtype = MEM_DDR2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		dimm->mtype = MEM_DDR3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	val = ti_edac_readl(edac, EMIF_ECC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	if (val & ECC_ENABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		dimm->edac_mode = EDAC_SECDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		dimm->edac_mode = EDAC_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static const struct of_device_id ti_edac_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	{ .compatible = "ti,emif-keystone", .data = (void *)EMIF_TYPE_K2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	{ .compatible = "ti,emif-dra7xx", .data = (void *)EMIF_TYPE_DRA7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) MODULE_DEVICE_TABLE(of, ti_edac_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static int _emif_get_id(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	const __be32 *addrp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	u32 addr, my_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	int my_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	addrp = of_get_address(node, 0, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	my_addr = (u32)of_translate_address(node, addrp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	for_each_matching_node(np, ti_edac_of_match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		if (np == node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		addrp = of_get_address(np, 0, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		addr = (u32)of_translate_address(np, addrp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		edac_printk(KERN_INFO, EDAC_MOD_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 			    "addr=%x, my_addr=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 			    addr, my_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		if (addr < my_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 			my_id++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	return my_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static int ti_edac_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	int error_irq = 0, ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	struct mem_ctl_info *mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	struct edac_mc_layer layers[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	const struct of_device_id *id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	struct ti_edac *edac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	int emif_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	id = of_match_device(ti_edac_of_match, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	if (!id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	reg = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	if (IS_ERR(reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		edac_printk(KERN_ERR, EDAC_MOD_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 			    "EMIF controller regs not defined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		return PTR_ERR(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	layers[0].type = EDAC_MC_LAYER_ALL_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	layers[0].size = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	/* Allocate ID number for our EMIF controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	emif_id = _emif_get_id(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	if (emif_id < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	mci = edac_mc_alloc(emif_id, 1, layers, sizeof(*edac));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	if (!mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	mci->pdev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	edac = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	edac->reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	platform_set_drvdata(pdev, mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	mci->mtype_cap = MEM_FLAG_DDR3 | MEM_FLAG_DDR2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	mci->edac_ctl_cap = EDAC_FLAG_SECDED | EDAC_FLAG_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	mci->mod_name = EDAC_MOD_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	mci->ctl_name = id->compatible;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	mci->dev_name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	/* Setup memory layout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	ti_edac_setup_dimm(mci, (u32)(id->data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	/* add EMIF ECC error handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	error_irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	if (error_irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		ret = error_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		edac_printk(KERN_ERR, EDAC_MOD_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 			    "EMIF irq number not defined.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	ret = devm_request_irq(dev, error_irq, ti_edac_isr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 			       "emif-edac-irq", mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		edac_printk(KERN_ERR, EDAC_MOD_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 			    "request_irq fail for EMIF EDAC irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	ret = edac_mc_add_mc(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		edac_printk(KERN_ERR, EDAC_MOD_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 			    "Failed to register mci: %d.\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	/* Generate an interrupt with each 1b error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	ti_edac_writel(edac, 1 << EMIF_1B_ECC_ERR_THRSH_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		       EMIF_1B_ECC_ERR_THRSH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	/* Enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	ti_edac_writel(edac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		       EMIF_1B_ECC_ERR | EMIF_2B_ECC_ERR | EMIF_WR_ECC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		       EMIF_IRQ_ENABLE_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static int ti_edac_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	struct mem_ctl_info *mci = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	edac_mc_del_mc(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static struct platform_driver ti_edac_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	.probe = ti_edac_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	.remove = ti_edac_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		   .name = EDAC_MOD_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		   .of_match_table = ti_edac_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) module_platform_driver(ti_edac_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) MODULE_AUTHOR("Texas Instruments Inc.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) MODULE_DESCRIPTION("EDAC Driver for Texas Instruments DDR3 MC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) MODULE_LICENSE("GPL v2");