^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * EDAC driver for Intel(R) Xeon(R) Skylake processors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2016, Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <asm/cpu_device_id.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/intel-family.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/mce.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "edac_module.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "skx_common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define EDAC_MOD_STR "skx_edac"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Debug macros
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define skx_printk(level, fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) edac_printk(level, "skx", fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define skx_mc_printk(mci, level, fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) edac_mc_chipset_printk(mci, level, "skx", fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static struct list_head *skx_edac_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static u64 skx_tolm, skx_tohm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static int skx_num_sockets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static unsigned int nvdimm_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MASK26 0x3FFFFFF /* Mask for 2^26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MASK29 0x1FFFFFFF /* Mask for 2^29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static struct skx_dev *get_skx_dev(struct pci_bus *bus, u8 idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct skx_dev *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) list_for_each_entry(d, skx_edac_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) if (d->seg == pci_domain_nr(bus) && d->bus[idx] == bus->number)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) return d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) enum munittype {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) CHAN0, CHAN1, CHAN2, SAD_ALL, UTIL_ALL, SAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ERRCHAN0, ERRCHAN1, ERRCHAN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct munit {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u16 did;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u16 devfn[SKX_NUM_IMC];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u8 busidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u8 per_socket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) enum munittype mtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * List of PCI device ids that we need together with some device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * number and function numbers to tell which memory controller the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * device belongs to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static const struct munit skx_all_munits[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { 0x2054, { }, 1, 1, SAD_ALL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { 0x2055, { }, 1, 1, UTIL_ALL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { 0x2040, { PCI_DEVFN(10, 0), PCI_DEVFN(12, 0) }, 2, 2, CHAN0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { 0x2044, { PCI_DEVFN(10, 4), PCI_DEVFN(12, 4) }, 2, 2, CHAN1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { 0x2048, { PCI_DEVFN(11, 0), PCI_DEVFN(13, 0) }, 2, 2, CHAN2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { 0x2043, { PCI_DEVFN(10, 3), PCI_DEVFN(12, 3) }, 2, 2, ERRCHAN0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { 0x2047, { PCI_DEVFN(10, 7), PCI_DEVFN(12, 7) }, 2, 2, ERRCHAN1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { 0x204b, { PCI_DEVFN(11, 3), PCI_DEVFN(13, 3) }, 2, 2, ERRCHAN2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { 0x208e, { }, 1, 0, SAD },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static int get_all_munits(const struct munit *m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct pci_dev *pdev, *prev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct skx_dev *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int i = 0, ndev = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) prev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) pdev = pci_get_device(PCI_VENDOR_ID_INTEL, m->did, prev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (!pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ndev++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (m->per_socket == SKX_NUM_IMC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) for (i = 0; i < SKX_NUM_IMC; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (m->devfn[i] == pdev->devfn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (i == SKX_NUM_IMC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) d = get_skx_dev(pdev->bus, m->busidx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (!d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Be sure that the device is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (unlikely(pci_enable_device(pdev) < 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) skx_printk(KERN_ERR, "Couldn't enable device %04x:%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) PCI_VENDOR_ID_INTEL, m->did);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) switch (m->mtype) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) case CHAN0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) case CHAN1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) case CHAN2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) pci_dev_get(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) d->imc[i].chan[m->mtype].cdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) case ERRCHAN0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) case ERRCHAN1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) case ERRCHAN2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) pci_dev_get(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) d->imc[i].chan[m->mtype - ERRCHAN0].edev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) case SAD_ALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) pci_dev_get(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) d->sad_all = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) case UTIL_ALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) pci_dev_get(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) d->util_all = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) case SAD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * one of these devices per core, including cores
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * that don't exist on this SKU. Ignore any that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * read a route table of zero, make sure all the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * non-zero values match.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) pci_read_config_dword(pdev, 0xB4, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (reg != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (d->mcroute == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) d->mcroute = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) } else if (d->mcroute != reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) skx_printk(KERN_ERR, "mcroute mismatch\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ndev--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) prev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) pci_dev_put(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static struct res_config skx_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .type = SKX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .decs_did = 0x2016,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .busno_cfg_offset = 0xcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static const struct x86_cpu_id skx_cpuids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SKYLAKE_X, X86_STEPPINGS(0x0, 0xf), &skx_cfg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) MODULE_DEVICE_TABLE(x86cpu, skx_cpuids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static bool skx_check_ecc(u32 mcmtr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return !!GET_BITFIELD(mcmtr, 2, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static int skx_get_dimm_config(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct skx_pvt *pvt = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u32 mtr, mcmtr, amap, mcddrtcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct skx_imc *imc = pvt->imc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct dimm_info *dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) int ndimms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* Only the mcmtr on the first channel is effective */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) pci_read_config_dword(imc->chan[0].cdev, 0x87c, &mcmtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) for (i = 0; i < SKX_NUM_CHANNELS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ndimms = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) pci_read_config_dword(imc->chan[i].cdev, 0x8C, &amap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) pci_read_config_dword(imc->chan[i].cdev, 0x400, &mcddrtcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) for (j = 0; j < SKX_NUM_DIMMS; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) dimm = edac_get_dimm(mci, i, j, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) pci_read_config_dword(imc->chan[i].cdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 0x80 + 4 * j, &mtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (IS_DIMM_PRESENT(mtr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ndimms += skx_get_dimm_info(mtr, mcmtr, amap, dimm, imc, i, j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) } else if (IS_NVDIMM_PRESENT(mcddrtcfg, j)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ndimms += skx_get_nvdimm_info(dimm, imc, i, j,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) EDAC_MOD_STR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) nvdimm_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (ndimms && !skx_check_ecc(mcmtr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) skx_printk(KERN_ERR, "ECC is disabled on imc %d\n", imc->mc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define SKX_MAX_SAD 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define SKX_GET_SAD(d, i, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) pci_read_config_dword((d)->sad_all, 0x60 + 8 * (i), &(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define SKX_GET_ILV(d, i, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) pci_read_config_dword((d)->sad_all, 0x64 + 8 * (i), &(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define SKX_SAD_MOD3MODE(sad) GET_BITFIELD((sad), 30, 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define SKX_SAD_MOD3(sad) GET_BITFIELD((sad), 27, 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define SKX_SAD_LIMIT(sad) (((u64)GET_BITFIELD((sad), 7, 26) << 26) | MASK26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define SKX_SAD_MOD3ASMOD2(sad) GET_BITFIELD((sad), 5, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define SKX_SAD_ATTR(sad) GET_BITFIELD((sad), 3, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define SKX_SAD_INTERLEAVE(sad) GET_BITFIELD((sad), 1, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define SKX_SAD_ENABLE(sad) GET_BITFIELD((sad), 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define SKX_ILV_REMOTE(tgt) (((tgt) & 8) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define SKX_ILV_TARGET(tgt) ((tgt) & 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static void skx_show_retry_rd_err_log(struct decoded_addr *res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) char *msg, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u32 log0, log1, log2, log3, log4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u32 corr0, corr1, corr2, corr3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct pci_dev *edev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) edev = res->dev->imc[res->imc].chan[res->channel].edev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) pci_read_config_dword(edev, 0x154, &log0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) pci_read_config_dword(edev, 0x148, &log1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) pci_read_config_dword(edev, 0x150, &log2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) pci_read_config_dword(edev, 0x15c, &log3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) pci_read_config_dword(edev, 0x114, &log4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) n = snprintf(msg, len, " retry_rd_err_log[%.8x %.8x %.8x %.8x %.8x]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) log0, log1, log2, log3, log4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) pci_read_config_dword(edev, 0x104, &corr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) pci_read_config_dword(edev, 0x108, &corr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) pci_read_config_dword(edev, 0x10c, &corr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) pci_read_config_dword(edev, 0x110, &corr3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (len - n > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) snprintf(msg + n, len - n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) " correrrcnt[%.4x %.4x %.4x %.4x %.4x %.4x %.4x %.4x]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) corr0 & 0xffff, corr0 >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) corr1 & 0xffff, corr1 >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) corr2 & 0xffff, corr2 >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) corr3 & 0xffff, corr3 >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static bool skx_sad_decode(struct decoded_addr *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct skx_dev *d = list_first_entry(skx_edac_list, typeof(*d), list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u64 addr = res->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) int i, idx, tgt, lchan, shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u32 sad, ilv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) u64 limit, prev_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) int remote = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* Simple sanity check for I/O space or out of range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (addr >= skx_tohm || (addr >= skx_tolm && addr < BIT_ULL(32))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) edac_dbg(0, "Address 0x%llx out of range\n", addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) restart:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) prev_limit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) for (i = 0; i < SKX_MAX_SAD; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) SKX_GET_SAD(d, i, sad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) limit = SKX_SAD_LIMIT(sad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (SKX_SAD_ENABLE(sad)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (addr >= prev_limit && addr <= limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) goto sad_found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) prev_limit = limit + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) edac_dbg(0, "No SAD entry for 0x%llx\n", addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) sad_found:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) SKX_GET_ILV(d, i, ilv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) switch (SKX_SAD_INTERLEAVE(sad)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) idx = GET_BITFIELD(addr, 6, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) idx = GET_BITFIELD(addr, 8, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) idx = GET_BITFIELD(addr, 12, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) idx = GET_BITFIELD(addr, 30, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) tgt = GET_BITFIELD(ilv, 4 * idx, 4 * idx + 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* If point to another node, find it and start over */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (SKX_ILV_REMOTE(tgt)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (remote) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) edac_dbg(0, "Double remote!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) remote = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) list_for_each_entry(d, skx_edac_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (d->imc[0].src_id == SKX_ILV_TARGET(tgt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) goto restart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) edac_dbg(0, "Can't find node %d\n", SKX_ILV_TARGET(tgt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (SKX_SAD_MOD3(sad) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) lchan = SKX_ILV_TARGET(tgt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) switch (SKX_SAD_MOD3MODE(sad)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) shift = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) shift = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) shift = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) edac_dbg(0, "illegal mod3mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) switch (SKX_SAD_MOD3ASMOD2(sad)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) lchan = (addr >> shift) % 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) lchan = (addr >> shift) % 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) lchan = (addr >> shift) % 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) lchan = (lchan << 1) | !lchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) lchan = ((addr >> shift) % 2) << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) lchan = (lchan << 1) | (SKX_ILV_TARGET(tgt) & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) res->dev = d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) res->socket = d->imc[0].src_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) res->imc = GET_BITFIELD(d->mcroute, lchan * 3, lchan * 3 + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) res->channel = GET_BITFIELD(d->mcroute, lchan * 2 + 18, lchan * 2 + 19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) edac_dbg(2, "0x%llx: socket=%d imc=%d channel=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) res->addr, res->socket, res->imc, res->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define SKX_MAX_TAD 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define SKX_GET_TADBASE(d, mc, i, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) pci_read_config_dword((d)->imc[mc].chan[0].cdev, 0x850 + 4 * (i), &(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define SKX_GET_TADWAYNESS(d, mc, i, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) pci_read_config_dword((d)->imc[mc].chan[0].cdev, 0x880 + 4 * (i), &(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define SKX_GET_TADCHNILVOFFSET(d, mc, ch, i, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) pci_read_config_dword((d)->imc[mc].chan[ch].cdev, 0x90 + 4 * (i), &(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define SKX_TAD_BASE(b) ((u64)GET_BITFIELD((b), 12, 31) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define SKX_TAD_SKT_GRAN(b) GET_BITFIELD((b), 4, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define SKX_TAD_CHN_GRAN(b) GET_BITFIELD((b), 6, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define SKX_TAD_LIMIT(b) (((u64)GET_BITFIELD((b), 12, 31) << 26) | MASK26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define SKX_TAD_OFFSET(b) ((u64)GET_BITFIELD((b), 4, 23) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define SKX_TAD_SKTWAYS(b) (1 << GET_BITFIELD((b), 10, 11))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define SKX_TAD_CHNWAYS(b) (GET_BITFIELD((b), 8, 9) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* which bit used for both socket and channel interleave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static int skx_granularity[] = { 6, 8, 12, 30 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static u64 skx_do_interleave(u64 addr, int shift, int ways, u64 lowbits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) addr >>= shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) addr /= ways;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) addr <<= shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return addr | (lowbits & ((1ull << shift) - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static bool skx_tad_decode(struct decoded_addr *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) u32 base, wayness, chnilvoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) int skt_interleave_bit, chn_interleave_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) u64 channel_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) for (i = 0; i < SKX_MAX_TAD; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) SKX_GET_TADBASE(res->dev, res->imc, i, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) SKX_GET_TADWAYNESS(res->dev, res->imc, i, wayness);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (SKX_TAD_BASE(base) <= res->addr && res->addr <= SKX_TAD_LIMIT(wayness))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) goto tad_found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) edac_dbg(0, "No TAD entry for 0x%llx\n", res->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) tad_found:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) res->sktways = SKX_TAD_SKTWAYS(wayness);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) res->chanways = SKX_TAD_CHNWAYS(wayness);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) skt_interleave_bit = skx_granularity[SKX_TAD_SKT_GRAN(base)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) chn_interleave_bit = skx_granularity[SKX_TAD_CHN_GRAN(base)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) SKX_GET_TADCHNILVOFFSET(res->dev, res->imc, res->channel, i, chnilvoffset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) channel_addr = res->addr - SKX_TAD_OFFSET(chnilvoffset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (res->chanways == 3 && skt_interleave_bit > chn_interleave_bit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* Must handle channel first, then socket */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) channel_addr = skx_do_interleave(channel_addr, chn_interleave_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) res->chanways, channel_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) channel_addr = skx_do_interleave(channel_addr, skt_interleave_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) res->sktways, channel_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* Handle socket then channel. Preserve low bits from original address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) channel_addr = skx_do_interleave(channel_addr, skt_interleave_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) res->sktways, res->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) channel_addr = skx_do_interleave(channel_addr, chn_interleave_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) res->chanways, res->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) res->chan_addr = channel_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) edac_dbg(2, "0x%llx: chan_addr=0x%llx sktways=%d chanways=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) res->addr, res->chan_addr, res->sktways, res->chanways);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define SKX_MAX_RIR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define SKX_GET_RIRWAYNESS(d, mc, ch, i, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) pci_read_config_dword((d)->imc[mc].chan[ch].cdev, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 0x108 + 4 * (i), &(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define SKX_GET_RIRILV(d, mc, ch, idx, i, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) pci_read_config_dword((d)->imc[mc].chan[ch].cdev, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 0x120 + 16 * (idx) + 4 * (i), &(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define SKX_RIR_VALID(b) GET_BITFIELD((b), 31, 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define SKX_RIR_LIMIT(b) (((u64)GET_BITFIELD((b), 1, 11) << 29) | MASK29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define SKX_RIR_WAYS(b) (1 << GET_BITFIELD((b), 28, 29))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define SKX_RIR_CHAN_RANK(b) GET_BITFIELD((b), 16, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define SKX_RIR_OFFSET(b) ((u64)(GET_BITFIELD((b), 2, 15) << 26))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static bool skx_rir_decode(struct decoded_addr *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) int i, idx, chan_rank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) u32 rirway, rirlv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) u64 rank_addr, prev_limit = 0, limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (res->dev->imc[res->imc].chan[res->channel].dimms[0].close_pg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) shift = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) shift = 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) for (i = 0; i < SKX_MAX_RIR; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) SKX_GET_RIRWAYNESS(res->dev, res->imc, res->channel, i, rirway);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) limit = SKX_RIR_LIMIT(rirway);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (SKX_RIR_VALID(rirway)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (prev_limit <= res->chan_addr &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) res->chan_addr <= limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) goto rir_found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) prev_limit = limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) edac_dbg(0, "No RIR entry for 0x%llx\n", res->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) rir_found:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) rank_addr = res->chan_addr >> shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) rank_addr /= SKX_RIR_WAYS(rirway);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) rank_addr <<= shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) rank_addr |= res->chan_addr & GENMASK_ULL(shift - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) res->rank_address = rank_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) idx = (res->chan_addr >> shift) % SKX_RIR_WAYS(rirway);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) SKX_GET_RIRILV(res->dev, res->imc, res->channel, idx, i, rirlv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) res->rank_address = rank_addr - SKX_RIR_OFFSET(rirlv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) chan_rank = SKX_RIR_CHAN_RANK(rirlv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) res->channel_rank = chan_rank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) res->dimm = chan_rank / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) res->rank = chan_rank % 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) edac_dbg(2, "0x%llx: dimm=%d rank=%d chan_rank=%d rank_addr=0x%llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) res->addr, res->dimm, res->rank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) res->channel_rank, res->rank_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static u8 skx_close_row[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 15, 16, 17, 18, 20, 21, 22, 28, 10, 11, 12, 13, 29, 30, 31, 32, 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static u8 skx_close_column[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 3, 4, 5, 14, 19, 23, 24, 25, 26, 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static u8 skx_open_row[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 14, 15, 16, 20, 28, 21, 22, 23, 24, 25, 26, 27, 29, 30, 31, 32, 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static u8 skx_open_column[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 3, 4, 5, 6, 7, 8, 9, 10, 11, 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static u8 skx_open_fine_column[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 3, 4, 5, 7, 8, 9, 10, 11, 12, 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static int skx_bits(u64 addr, int nbits, u8 *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) int i, res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) for (i = 0; i < nbits; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) res |= ((addr >> bits[i]) & 1) << i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static int skx_bank_bits(u64 addr, int b0, int b1, int do_xor, int x0, int x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) int ret = GET_BITFIELD(addr, b0, b0) | (GET_BITFIELD(addr, b1, b1) << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (do_xor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) ret ^= GET_BITFIELD(addr, x0, x0) | (GET_BITFIELD(addr, x1, x1) << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static bool skx_mad_decode(struct decoded_addr *r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct skx_dimm *dimm = &r->dev->imc[r->imc].chan[r->channel].dimms[r->dimm];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) int bg0 = dimm->fine_grain_bank ? 6 : 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (dimm->close_pg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) r->row = skx_bits(r->rank_address, dimm->rowbits, skx_close_row);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) r->column = skx_bits(r->rank_address, dimm->colbits, skx_close_column);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) r->column |= 0x400; /* C10 is autoprecharge, always set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) r->bank_address = skx_bank_bits(r->rank_address, 8, 9, dimm->bank_xor_enable, 22, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) r->bank_group = skx_bank_bits(r->rank_address, 6, 7, dimm->bank_xor_enable, 20, 21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) r->row = skx_bits(r->rank_address, dimm->rowbits, skx_open_row);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (dimm->fine_grain_bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) r->column = skx_bits(r->rank_address, dimm->colbits, skx_open_fine_column);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) r->column = skx_bits(r->rank_address, dimm->colbits, skx_open_column);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) r->bank_address = skx_bank_bits(r->rank_address, 18, 19, dimm->bank_xor_enable, 22, 23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) r->bank_group = skx_bank_bits(r->rank_address, bg0, 17, dimm->bank_xor_enable, 20, 21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) r->row &= (1u << dimm->rowbits) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) edac_dbg(2, "0x%llx: row=0x%x col=0x%x bank_addr=%d bank_group=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) r->addr, r->row, r->column, r->bank_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) r->bank_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static bool skx_decode(struct decoded_addr *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return skx_sad_decode(res) && skx_tad_decode(res) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) skx_rir_decode(res) && skx_mad_decode(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static struct notifier_block skx_mce_dec = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .notifier_call = skx_mce_check_error,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .priority = MCE_PRIO_EDAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #ifdef CONFIG_EDAC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * Debug feature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * Exercise the address decode logic by writing an address to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * /sys/kernel/debug/edac/skx_test/addr.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static struct dentry *skx_test;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static int debugfs_u64_set(void *data, u64 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct mce m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) pr_warn_once("Fake error to 0x%llx injected via debugfs\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) memset(&m, 0, sizeof(m));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /* ADDRV + MemRd + Unknown channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) m.status = MCI_STATUS_ADDRV + 0x90;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /* One corrected error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) m.status |= BIT_ULL(MCI_STATUS_CEC_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) m.addr = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) skx_mce_check_error(NULL, 0, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) DEFINE_SIMPLE_ATTRIBUTE(fops_u64_wo, NULL, debugfs_u64_set, "%llu\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static void setup_skx_debug(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) skx_test = edac_debugfs_create_dir("skx_test");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (!skx_test)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (!edac_debugfs_create_file("addr", 0200, skx_test,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) NULL, &fops_u64_wo)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) debugfs_remove(skx_test);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) skx_test = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static void teardown_skx_debug(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) debugfs_remove_recursive(skx_test);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static inline void setup_skx_debug(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static inline void teardown_skx_debug(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #endif /*CONFIG_EDAC_DEBUG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * skx_init:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * make sure we are running on the correct cpu model
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * search for all the devices we need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * check which DIMMs are present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static int __init skx_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) const struct x86_cpu_id *id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) struct res_config *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) const struct munit *m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) const char *owner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) int rc = 0, i, off[3] = {0xd0, 0xd4, 0xd8};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) u8 mc = 0, src_id, node_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) struct skx_dev *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) edac_dbg(2, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) owner = edac_get_owner();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (cpu_feature_enabled(X86_FEATURE_HYPERVISOR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) id = x86_match_cpu(skx_cpuids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (!id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) cfg = (struct res_config *)id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) rc = skx_get_hi_lo(0x2034, off, &skx_tolm, &skx_tohm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) rc = skx_get_all_bus_mappings(cfg, &skx_edac_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (rc == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) edac_dbg(2, "No memory controllers found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) skx_num_sockets = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) for (m = skx_all_munits; m->did; m++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) rc = get_all_munits(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (rc != m->per_socket * skx_num_sockets) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) edac_dbg(2, "Expected %d, got %d of 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) m->per_socket * skx_num_sockets, rc, m->did);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) list_for_each_entry(d, skx_edac_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) rc = skx_get_src_id(d, 0xf0, &src_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) rc = skx_get_node_id(d, &node_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) edac_dbg(2, "src_id=%d node_id=%d\n", src_id, node_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) for (i = 0; i < SKX_NUM_IMC; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) d->imc[i].mc = mc++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) d->imc[i].lmc = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) d->imc[i].src_id = src_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) d->imc[i].node_id = node_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) rc = skx_register_mci(&d->imc[i], d->imc[i].chan[0].cdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) "Skylake Socket", EDAC_MOD_STR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) skx_get_dimm_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) skx_set_decode(skx_decode, skx_show_retry_rd_err_log);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (nvdimm_count && skx_adxl_get() == -ENODEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) skx_printk(KERN_NOTICE, "Only decoding DDR4 address!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) /* Ensure that the OPSTATE is set correctly for POLL or NMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) opstate_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) setup_skx_debug();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) mce_register_decode_chain(&skx_mce_dec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) skx_remove();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static void __exit skx_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) edac_dbg(2, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) mce_unregister_decode_chain(&skx_mce_dec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) teardown_skx_debug();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (nvdimm_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) skx_adxl_put();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) skx_remove();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) module_init(skx_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) module_exit(skx_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) module_param(edac_op_state, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) MODULE_AUTHOR("Tony Luck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) MODULE_DESCRIPTION("MC Driver for Intel Skylake server processors");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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