^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This driver supports the memory controllers found on the Intel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * processor family Sandy Bridge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2011 by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Mauro Carvalho Chehab
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pci_ids.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/edac.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mmzone.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/bitmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/math64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/cpu_device_id.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/intel-family.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/mce.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "edac_module.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Static vars */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static LIST_HEAD(sbridge_edac_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * Alter this version for the module when modifications are made
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SBRIDGE_REVISION " Ver: 1.1.2 "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define EDAC_MOD_STR "sb_edac"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * Debug macros
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define sbridge_printk(level, fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) edac_printk(level, "sbridge", fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define sbridge_mc_printk(mci, level, fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) edac_mc_chipset_printk(mci, level, "sbridge", fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * Get a bit field at register value <v>, from bit <lo> to bit <hi>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define GET_BITFIELD(v, lo, hi) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) (((v) & GENMASK_ULL(hi, lo)) >> (lo))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Devices 12 Function 6, Offsets 0x80 to 0xcc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static const u32 sbridge_dram_rule[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 0x80, 0x88, 0x90, 0x98, 0xa0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 0xa8, 0xb0, 0xb8, 0xc0, 0xc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static const u32 ibridge_dram_rule[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 0x60, 0x68, 0x70, 0x78, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 0x88, 0x90, 0x98, 0xa0, 0xa8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 0xb0, 0xb8, 0xc0, 0xc8, 0xd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 0xd8, 0xe0, 0xe8, 0xf0, 0xf8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static const u32 knl_dram_rule[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 0x60, 0x68, 0x70, 0x78, 0x80, /* 0-4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 0x88, 0x90, 0x98, 0xa0, 0xa8, /* 5-9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 0xb0, 0xb8, 0xc0, 0xc8, 0xd0, /* 10-14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 0xd8, 0xe0, 0xe8, 0xf0, 0xf8, /* 15-19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 0x100, 0x108, 0x110, 0x118, /* 20-23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DRAM_RULE_ENABLE(reg) GET_BITFIELD(reg, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define A7MODE(reg) GET_BITFIELD(reg, 26, 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static char *show_dram_attr(u32 attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return "DRAM";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return "MMCFG";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return "NXM";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return "unknown";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static const u32 sbridge_interleave_list[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) 0x84, 0x8c, 0x94, 0x9c, 0xa4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) 0xac, 0xb4, 0xbc, 0xc4, 0xcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static const u32 ibridge_interleave_list[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) 0x64, 0x6c, 0x74, 0x7c, 0x84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) 0x8c, 0x94, 0x9c, 0xa4, 0xac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 0xb4, 0xbc, 0xc4, 0xcc, 0xd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 0xdc, 0xe4, 0xec, 0xf4, 0xfc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static const u32 knl_interleave_list[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 0x64, 0x6c, 0x74, 0x7c, 0x84, /* 0-4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 0x8c, 0x94, 0x9c, 0xa4, 0xac, /* 5-9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 0xb4, 0xbc, 0xc4, 0xcc, 0xd4, /* 10-14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 0xdc, 0xe4, 0xec, 0xf4, 0xfc, /* 15-19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 0x104, 0x10c, 0x114, 0x11c, /* 20-23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MAX_INTERLEAVE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) (max_t(unsigned int, ARRAY_SIZE(sbridge_interleave_list), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) max_t(unsigned int, ARRAY_SIZE(ibridge_interleave_list), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ARRAY_SIZE(knl_interleave_list))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct interleave_pkg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned char start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned char end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const struct interleave_pkg sbridge_interleave_pkg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { 0, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { 3, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { 8, 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { 11, 13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { 16, 18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { 19, 21 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { 24, 26 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { 27, 29 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static const struct interleave_pkg ibridge_interleave_pkg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { 0, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { 4, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { 8, 11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { 12, 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { 16, 19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { 20, 23 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { 24, 27 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { 28, 31 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static inline int sad_pkg(const struct interleave_pkg *table, u32 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int interleave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return GET_BITFIELD(reg, table[interleave].start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) table[interleave].end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* Devices 12 Function 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define TOLM 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define TOHM 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define HASWELL_TOLM 0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define HASWELL_TOHM_0 0xd4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define HASWELL_TOHM_1 0xd8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define KNL_TOLM 0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define KNL_TOHM_0 0xd4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define KNL_TOHM_1 0xd8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define GET_TOLM(reg) ((GET_BITFIELD(reg, 0, 3) << 28) | 0x3ffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define GET_TOHM(reg) ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* Device 13 Function 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define SAD_TARGET 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define SOURCE_ID(reg) GET_BITFIELD(reg, 9, 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define SOURCE_ID_KNL(reg) GET_BITFIELD(reg, 12, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define SAD_CONTROL 0xf4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* Device 14 function 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static const u32 tad_dram_rule[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 0x40, 0x44, 0x48, 0x4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 0x50, 0x54, 0x58, 0x5c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 0x60, 0x64, 0x68, 0x6c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define MAX_TAD ARRAY_SIZE(tad_dram_rule)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define TAD_LIMIT(reg) ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define TAD_SOCK(reg) GET_BITFIELD(reg, 10, 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define TAD_CH(reg) GET_BITFIELD(reg, 8, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define TAD_TGT3(reg) GET_BITFIELD(reg, 6, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define TAD_TGT2(reg) GET_BITFIELD(reg, 4, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define TAD_TGT1(reg) GET_BITFIELD(reg, 2, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define TAD_TGT0(reg) GET_BITFIELD(reg, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* Device 15, function 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define MCMTR 0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define KNL_MCMTR 0x624
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define IS_ECC_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 2, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define IS_LOCKSTEP_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define IS_CLOSE_PG(mcmtr) GET_BITFIELD(mcmtr, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* Device 15, function 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define RASENABLES 0xac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define IS_MIRROR_ENABLED(reg) GET_BITFIELD(reg, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* Device 15, functions 2-5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static const int mtr_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 0x80, 0x84, 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static const int knl_mtr_reg = 0xb60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define RANK_DISABLE(mtr) GET_BITFIELD(mtr, 16, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define IS_DIMM_PRESENT(mtr) GET_BITFIELD(mtr, 14, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define RANK_CNT_BITS(mtr) GET_BITFIELD(mtr, 12, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define RANK_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 2, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define COL_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static const u32 tad_ch_nilv_offset[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 0x90, 0x94, 0x98, 0x9c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 0xa0, 0xa4, 0xa8, 0xac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 0xb0, 0xb4, 0xb8, 0xbc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define CHN_IDX_OFFSET(reg) GET_BITFIELD(reg, 28, 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define TAD_OFFSET(reg) (GET_BITFIELD(reg, 6, 25) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static const u32 rir_way_limit[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 0x108, 0x10c, 0x110, 0x114, 0x118,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define IS_RIR_VALID(reg) GET_BITFIELD(reg, 31, 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define RIR_WAY(reg) GET_BITFIELD(reg, 28, 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define MAX_RIR_WAY 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static const u32 rir_offset[MAX_RIR_RANGES][MAX_RIR_WAY] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) { 0x120, 0x124, 0x128, 0x12c, 0x130, 0x134, 0x138, 0x13c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) { 0x140, 0x144, 0x148, 0x14c, 0x150, 0x154, 0x158, 0x15c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) { 0x160, 0x164, 0x168, 0x16c, 0x170, 0x174, 0x178, 0x17c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) { 0x180, 0x184, 0x188, 0x18c, 0x190, 0x194, 0x198, 0x19c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) { 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define RIR_RNK_TGT(type, reg) (((type) == BROADWELL) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) GET_BITFIELD(reg, 20, 23) : GET_BITFIELD(reg, 16, 19))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define RIR_OFFSET(type, reg) (((type) == HASWELL || (type) == BROADWELL) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) GET_BITFIELD(reg, 2, 15) : GET_BITFIELD(reg, 2, 14))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* Device 16, functions 2-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * FIXME: Implement the error count reads directly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define RANK_ODD_OV(reg) GET_BITFIELD(reg, 31, 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define RANK_ODD_ERR_CNT(reg) GET_BITFIELD(reg, 16, 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define RANK_EVEN_OV(reg) GET_BITFIELD(reg, 15, 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define RANK_EVEN_ERR_CNT(reg) GET_BITFIELD(reg, 0, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #if 0 /* Currently unused*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static const u32 correrrcnt[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 0x104, 0x108, 0x10c, 0x110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static const u32 correrrthrsld[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 0x11c, 0x120, 0x124, 0x128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define RANK_ODD_ERR_THRSLD(reg) GET_BITFIELD(reg, 16, 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define RANK_EVEN_ERR_THRSLD(reg) GET_BITFIELD(reg, 0, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* Device 17, function 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define SB_RANK_CFG_A 0x0328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define IB_RANK_CFG_A 0x0320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * sbridge structs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define NUM_CHANNELS 6 /* Max channels per MC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define MAX_DIMMS 3 /* Max DIMMS per channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define KNL_MAX_CHAS 38 /* KNL max num. of Cache Home Agents */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define KNL_MAX_CHANNELS 6 /* KNL max num. of PCI channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define KNL_MAX_EDCS 8 /* Embedded DRAM controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define CHANNEL_UNSPECIFIED 0xf /* Intel IA32 SDM 15-14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) enum type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) SANDY_BRIDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) IVY_BRIDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) HASWELL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) BROADWELL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) KNIGHTS_LANDING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) enum domain {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) IMC0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) IMC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) SOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) enum mirroring_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) NON_MIRRORING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ADDR_RANGE_MIRRORING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) FULL_MIRRORING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct sbridge_pvt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct sbridge_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) enum type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) u32 mcmtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) u32 rankcfgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) u64 (*get_tolm)(struct sbridge_pvt *pvt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) u64 (*get_tohm)(struct sbridge_pvt *pvt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) u64 (*rir_limit)(u32 reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) u64 (*sad_limit)(u32 reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u32 (*interleave_mode)(u32 reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u32 (*dram_attr)(u32 reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) const u32 *dram_rule;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) const u32 *interleave_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) const struct interleave_pkg *interleave_pkg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u8 max_sad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u8 (*get_node_id)(struct sbridge_pvt *pvt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u8 (*get_ha)(u8 bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) enum mem_type (*get_memory_type)(struct sbridge_pvt *pvt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) enum dev_type (*get_width)(struct sbridge_pvt *pvt, u32 mtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct pci_dev *pci_vtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct sbridge_channel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u32 ranks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u32 dimms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct pci_id_descr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) int dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) int optional;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) enum domain dom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct pci_id_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) const struct pci_id_descr *descr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) int n_devs_per_imc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) int n_devs_per_sock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) int n_imcs_per_sock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) enum type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct sbridge_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) int seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u8 bus, mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) u8 node_id, source_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct pci_dev **pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) enum domain dom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) int n_devs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) int i_devs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct mem_ctl_info *mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct knl_pvt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct pci_dev *pci_cha[KNL_MAX_CHAS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct pci_dev *pci_channel[KNL_MAX_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct pci_dev *pci_mc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct pci_dev *pci_mc1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct pci_dev *pci_mc0_misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct pci_dev *pci_mc1_misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct pci_dev *pci_mc_info; /* tolm, tohm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct sbridge_pvt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* Devices per socket */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct pci_dev *pci_ddrio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct pci_dev *pci_sad0, *pci_sad1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct pci_dev *pci_br0, *pci_br1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* Devices per memory controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct pci_dev *pci_ha, *pci_ta, *pci_ras;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct pci_dev *pci_tad[NUM_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct sbridge_dev *sbridge_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct sbridge_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct sbridge_channel channel[NUM_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* Memory type detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) bool is_cur_addr_mirrored, is_lockstep, is_close_pg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) bool is_chan_hash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) enum mirroring_mode mirror_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* Memory description */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) u64 tolm, tohm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct knl_pvt knl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define PCI_DESCR(device_id, opt, domain) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .dev_id = (device_id), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .optional = opt, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .dom = domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static const struct pci_id_descr pci_dev_descr_sbridge[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* Processor Home Agent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0, 0, IMC0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* Memory controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA, 0, IMC0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS, 0, IMC0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0, 0, IMC0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1, 0, IMC0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2, 0, IMC0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3, 0, IMC0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO, 1, SOCK) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* System Address Decoder */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0, 0, SOCK) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1, 0, SOCK) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* Broadcast Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_BR, 0, SOCK) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define PCI_ID_TABLE_ENTRY(A, N, M, T) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .descr = A, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .n_devs_per_imc = N, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .n_devs_per_sock = ARRAY_SIZE(A), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .n_imcs_per_sock = M, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .type = T \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static const struct pci_id_table pci_dev_descr_sbridge_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge, ARRAY_SIZE(pci_dev_descr_sbridge), 1, SANDY_BRIDGE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {0,} /* 0 terminated list. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* This changes depending if 1HA or 2HA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * 1HA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * 0x0eb8 (17.0) is DDRIO0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * 2HA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * 0x0ebc (17.4) is DDRIO0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0 0x0eb8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0 0x0ebc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* pci ids */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0 0x0ea0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA 0x0ea8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS 0x0e71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0 0x0eaa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1 0x0eab
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2 0x0eac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3 0x0ead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define PCI_DEVICE_ID_INTEL_IBRIDGE_SAD 0x0ec8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR0 0x0ec9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR1 0x0eca
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1 0x0e60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA 0x0e68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS 0x0e79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0 0x0e6a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1 0x0e6b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2 0x0e6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3 0x0e6d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static const struct pci_id_descr pci_dev_descr_ibridge[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* Processor Home Agent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0, 0, IMC0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1, 1, IMC1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* Memory controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA, 0, IMC0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS, 0, IMC0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0, 0, IMC0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1, 0, IMC0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2, 0, IMC0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3, 0, IMC0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* Optional, mode 2HA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA, 1, IMC1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS, 1, IMC1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0, 1, IMC1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1, 1, IMC1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2, 1, IMC1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3, 1, IMC1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0, 1, SOCK) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0, 1, SOCK) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* System Address Decoder */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_SAD, 0, SOCK) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* Broadcast Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR0, 1, SOCK) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR1, 0, SOCK) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static const struct pci_id_table pci_dev_descr_ibridge_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) PCI_ID_TABLE_ENTRY(pci_dev_descr_ibridge, 12, 2, IVY_BRIDGE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {0,} /* 0 terminated list. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* Haswell support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* EN processor:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * - 1 IMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * - 3 DDR3 channels, 2 DPC per channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * EP processor:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * - 1 or 2 IMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * - 4 DDR4 channels, 3 DPC per channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * EP 4S processor:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * - 2 IMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * - 4 DDR4 channels, 3 DPC per channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * EX processor:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * - 2 IMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * - each IMC interfaces with a SMI 2 channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * - each SMI channel interfaces with a scalable memory buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define HASWELL_DDRCRCLKCONTROLS 0xa10 /* Ditto on Broadwell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define HASWELL_HASYSDEFEATURE2 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC 0x2f28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0 0x2fa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1 0x2f60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA 0x2fa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TM 0x2f71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA 0x2f68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TM 0x2f79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0 0x2ffc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1 0x2ffd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0 0x2faa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1 0x2fab
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2 0x2fac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3 0x2fad
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0 0x2f6a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1 0x2f6b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2 0x2f6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3 0x2f6d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0 0x2fbd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1 0x2fbf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2 0x2fb9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3 0x2fbb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static const struct pci_id_descr pci_dev_descr_haswell[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* first item must be the HA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0, 0, IMC0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1, 1, IMC1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA, 0, IMC0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TM, 0, IMC0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0, 0, IMC0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1, 0, IMC0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2, 1, IMC0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3, 1, IMC0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA, 1, IMC1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TM, 1, IMC1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0, 1, IMC1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1, 1, IMC1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2, 1, IMC1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3, 1, IMC1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0, 0, SOCK) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1, 0, SOCK) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0, 1, SOCK) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1, 1, SOCK) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2, 1, SOCK) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3, 1, SOCK) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static const struct pci_id_table pci_dev_descr_haswell_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) PCI_ID_TABLE_ENTRY(pci_dev_descr_haswell, 13, 2, HASWELL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {0,} /* 0 terminated list. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* Knight's Landing Support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) * KNL's memory channels are swizzled between memory controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) * MC0 is mapped to CH3,4,5 and MC1 is mapped to CH0,1,2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define knl_channel_remap(mc, chan) ((mc) ? (chan) : (chan) + 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /* Memory controller, TAD tables, error injection - 2-8-0, 2-9-0 (2 of these) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define PCI_DEVICE_ID_INTEL_KNL_IMC_MC 0x7840
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* DRAM channel stuff; bank addrs, dimmmtr, etc.. 2-8-2 - 2-9-4 (6 of these) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define PCI_DEVICE_ID_INTEL_KNL_IMC_CHAN 0x7843
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* kdrwdbu TAD limits/offsets, MCMTR - 2-10-1, 2-11-1 (2 of these) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define PCI_DEVICE_ID_INTEL_KNL_IMC_TA 0x7844
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* CHA broadcast registers, dram rules - 1-29-0 (1 of these) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0 0x782a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /* SAD target - 1-29-1 (1 of these) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1 0x782b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /* Caching / Home Agent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define PCI_DEVICE_ID_INTEL_KNL_IMC_CHA 0x782c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /* Device with TOLM and TOHM, 0-5-0 (1 of these) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM 0x7810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * KNL differs from SB, IB, and Haswell in that it has multiple
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * instances of the same device with the same device ID, so we handle that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * by creating as many copies in the table as we expect to find.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * (Like device ID must be grouped together.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static const struct pci_id_descr pci_dev_descr_knl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) [0 ... 1] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_MC, 0, IMC0)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) [2 ... 7] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_CHAN, 0, IMC0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) [8] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_TA, 0, IMC0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) [9] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM, 0, IMC0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) [10] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0, 0, SOCK) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) [11] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1, 0, SOCK) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) [12 ... 49] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_CHA, 0, SOCK) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static const struct pci_id_table pci_dev_descr_knl_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) PCI_ID_TABLE_ENTRY(pci_dev_descr_knl, ARRAY_SIZE(pci_dev_descr_knl), 1, KNIGHTS_LANDING),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) {0,}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * Broadwell support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * DE processor:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * - 1 IMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * - 2 DDR3 channels, 2 DPC per channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * EP processor:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * - 1 or 2 IMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * - 4 DDR4 channels, 3 DPC per channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * EP 4S processor:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * - 2 IMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * - 4 DDR4 channels, 3 DPC per channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * EX processor:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) * - 2 IMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * - each IMC interfaces with a SMI 2 channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * - each SMI channel interfaces with a scalable memory buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC 0x6f28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0 0x6fa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1 0x6f60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA 0x6fa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TM 0x6f71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA 0x6f68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TM 0x6f79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0 0x6ffc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1 0x6ffd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0 0x6faa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1 0x6fab
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2 0x6fac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3 0x6fad
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0 0x6f6a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1 0x6f6b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2 0x6f6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3 0x6f6d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0 0x6faf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static const struct pci_id_descr pci_dev_descr_broadwell[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /* first item must be the HA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0, 0, IMC0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1, 1, IMC1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA, 0, IMC0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TM, 0, IMC0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0, 0, IMC0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1, 0, IMC0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2, 1, IMC0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3, 1, IMC0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA, 1, IMC1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TM, 1, IMC1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0, 1, IMC1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1, 1, IMC1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2, 1, IMC1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3, 1, IMC1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0, 0, SOCK) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1, 0, SOCK) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0, 1, SOCK) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) static const struct pci_id_table pci_dev_descr_broadwell_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) PCI_ID_TABLE_ENTRY(pci_dev_descr_broadwell, 10, 2, BROADWELL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) {0,} /* 0 terminated list. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) Ancillary status routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static inline int numrank(enum type type, u32 mtr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) int ranks = (1 << RANK_CNT_BITS(mtr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) int max = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (type == HASWELL || type == BROADWELL || type == KNIGHTS_LANDING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) max = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (ranks > max) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) edac_dbg(0, "Invalid number of ranks: %d (max = %i) raw value = %x (%04x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) ranks, max, (unsigned int)RANK_CNT_BITS(mtr), mtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) return ranks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static inline int numrow(u32 mtr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) int rows = (RANK_WIDTH_BITS(mtr) + 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (rows < 13 || rows > 18) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) edac_dbg(0, "Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return 1 << rows;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static inline int numcol(u32 mtr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) int cols = (COL_WIDTH_BITS(mtr) + 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (cols > 12) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) edac_dbg(0, "Invalid number of cols: %d (max = 4) raw value = %x (%04x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return 1 << cols;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static struct sbridge_dev *get_sbridge_dev(int seg, u8 bus, enum domain dom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) int multi_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) struct sbridge_dev *prev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) struct sbridge_dev *sbridge_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) * If we have devices scattered across several busses that pertain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) * to the same memory controller, we'll lump them all together.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (multi_bus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return list_first_entry_or_null(&sbridge_edac_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) struct sbridge_dev, list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) sbridge_dev = list_entry(prev ? prev->list.next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) : sbridge_edac_list.next, struct sbridge_dev, list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) list_for_each_entry_from(sbridge_dev, &sbridge_edac_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if ((sbridge_dev->seg == seg) && (sbridge_dev->bus == bus) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) (dom == SOCK || dom == sbridge_dev->dom))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) return sbridge_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) static struct sbridge_dev *alloc_sbridge_dev(int seg, u8 bus, enum domain dom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) const struct pci_id_table *table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) struct sbridge_dev *sbridge_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) sbridge_dev = kzalloc(sizeof(*sbridge_dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (!sbridge_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) sbridge_dev->pdev = kcalloc(table->n_devs_per_imc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) sizeof(*sbridge_dev->pdev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (!sbridge_dev->pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) kfree(sbridge_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) sbridge_dev->seg = seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) sbridge_dev->bus = bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) sbridge_dev->dom = dom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) sbridge_dev->n_devs = table->n_devs_per_imc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) list_add_tail(&sbridge_dev->list, &sbridge_edac_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) return sbridge_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static void free_sbridge_dev(struct sbridge_dev *sbridge_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) list_del(&sbridge_dev->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) kfree(sbridge_dev->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) kfree(sbridge_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static u64 sbridge_get_tolm(struct sbridge_pvt *pvt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) /* Address range is 32:28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) pci_read_config_dword(pvt->pci_sad1, TOLM, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return GET_TOLM(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static u64 sbridge_get_tohm(struct sbridge_pvt *pvt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) pci_read_config_dword(pvt->pci_sad1, TOHM, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return GET_TOHM(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static u64 ibridge_get_tolm(struct sbridge_pvt *pvt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) pci_read_config_dword(pvt->pci_br1, TOLM, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) return GET_TOLM(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static u64 ibridge_get_tohm(struct sbridge_pvt *pvt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) pci_read_config_dword(pvt->pci_br1, TOHM, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) return GET_TOHM(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static u64 rir_limit(u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return ((u64)GET_BITFIELD(reg, 1, 10) << 29) | 0x1fffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) static u64 sad_limit(u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return (GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static u32 interleave_mode(u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return GET_BITFIELD(reg, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static u32 dram_attr(u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) return GET_BITFIELD(reg, 2, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) static u64 knl_sad_limit(u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) return (GET_BITFIELD(reg, 7, 26) << 26) | 0x3ffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) static u32 knl_interleave_mode(u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) return GET_BITFIELD(reg, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static const char * const knl_intlv_mode[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) "[8:6]", "[10:8]", "[14:12]", "[32:30]"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) static const char *get_intlv_mode_str(u32 reg, enum type t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (t == KNIGHTS_LANDING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) return knl_intlv_mode[knl_interleave_mode(reg)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) return interleave_mode(reg) ? "[8:6]" : "[8:6]XOR[18:16]";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) static u32 dram_attr_knl(u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) return GET_BITFIELD(reg, 3, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) static enum mem_type get_memory_type(struct sbridge_pvt *pvt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) enum mem_type mtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (pvt->pci_ddrio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) pci_read_config_dword(pvt->pci_ddrio, pvt->info.rankcfgr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (GET_BITFIELD(reg, 11, 11))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) /* FIXME: Can also be LRDIMM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) mtype = MEM_RDDR3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) mtype = MEM_DDR3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) mtype = MEM_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) return mtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) static enum mem_type haswell_get_memory_type(struct sbridge_pvt *pvt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) bool registered = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) enum mem_type mtype = MEM_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (!pvt->pci_ddrio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) pci_read_config_dword(pvt->pci_ddrio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) HASWELL_DDRCRCLKCONTROLS, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) /* Is_Rdimm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (GET_BITFIELD(reg, 16, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) registered = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) pci_read_config_dword(pvt->pci_ta, MCMTR, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if (GET_BITFIELD(reg, 14, 14)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) if (registered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) mtype = MEM_RDDR4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) mtype = MEM_DDR4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (registered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) mtype = MEM_RDDR3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) mtype = MEM_DDR3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) return mtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) static enum dev_type knl_get_width(struct sbridge_pvt *pvt, u32 mtr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) /* for KNL value is fixed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) return DEV_X16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) static enum dev_type sbridge_get_width(struct sbridge_pvt *pvt, u32 mtr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) /* there's no way to figure out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) return DEV_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) static enum dev_type __ibridge_get_width(u32 mtr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) enum dev_type type = DEV_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) switch (mtr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) type = DEV_X16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) type = DEV_X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) type = DEV_X4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) return type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) static enum dev_type ibridge_get_width(struct sbridge_pvt *pvt, u32 mtr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) * ddr3_width on the documentation but also valid for DDR4 on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) * Haswell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) return __ibridge_get_width(GET_BITFIELD(mtr, 7, 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static enum dev_type broadwell_get_width(struct sbridge_pvt *pvt, u32 mtr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) /* ddr3_width on the documentation but also valid for DDR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) return __ibridge_get_width(GET_BITFIELD(mtr, 8, 9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) static enum mem_type knl_get_memory_type(struct sbridge_pvt *pvt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) /* DDR4 RDIMMS and LRDIMMS are supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) return MEM_RDDR4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) static u8 get_node_id(struct sbridge_pvt *pvt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) return GET_BITFIELD(reg, 0, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) static u8 haswell_get_node_id(struct sbridge_pvt *pvt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) return GET_BITFIELD(reg, 0, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) static u8 knl_get_node_id(struct sbridge_pvt *pvt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) return GET_BITFIELD(reg, 0, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) * Use the reporting bank number to determine which memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) * controller (also known as "ha" for "home agent"). Sandy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) * Bridge only has one memory controller per socket, so the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) * answer is always zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) static u8 sbridge_get_ha(u8 bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) * On Ivy Bridge, Haswell and Broadwell the error may be in a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) * home agent bank (7, 8), or one of the per-channel memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) * controller banks (9 .. 16).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) static u8 ibridge_get_ha(u8 bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) switch (bank) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) case 7 ... 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) return bank - 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) case 9 ... 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) return (bank - 9) / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) return 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) /* Not used, but included for safety/symmetry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) static u8 knl_get_ha(u8 bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) return 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) static u64 haswell_get_tolm(struct sbridge_pvt *pvt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOLM, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) static u64 haswell_get_tohm(struct sbridge_pvt *pvt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) u64 rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_0, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) rc = GET_BITFIELD(reg, 26, 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) rc = ((reg << 6) | rc) << 26;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) return rc | 0x3ffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) static u64 knl_get_tolm(struct sbridge_pvt *pvt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOLM, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) static u64 knl_get_tohm(struct sbridge_pvt *pvt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) u64 rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) u32 reg_lo, reg_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_0, ®_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_1, ®_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) rc = ((u64)reg_hi << 32) | reg_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) return rc | 0x3ffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) static u64 haswell_rir_limit(u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) return (((u64)GET_BITFIELD(reg, 1, 11) + 1) << 29) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) static inline u8 sad_pkg_socket(u8 pkg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) /* on Ivy Bridge, nodeID is SASS, where A is HA and S is node id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) return ((pkg >> 3) << 2) | (pkg & 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) static inline u8 sad_pkg_ha(u8 pkg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) return (pkg >> 2) & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) static int haswell_chan_hash(int idx, u64 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) * XOR even bits from 12:26 to bit0 of idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) * odd bits from 13:27 to bit1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) for (i = 12; i < 28; i += 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) idx ^= (addr >> i) & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) return idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) /* Low bits of TAD limit, and some metadata. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) static const u32 knl_tad_dram_limit_lo[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) 0x400, 0x500, 0x600, 0x700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) 0x800, 0x900, 0xa00, 0xb00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) /* Low bits of TAD offset. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) static const u32 knl_tad_dram_offset_lo[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) 0x404, 0x504, 0x604, 0x704,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) 0x804, 0x904, 0xa04, 0xb04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) /* High 16 bits of TAD limit and offset. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) static const u32 knl_tad_dram_hi[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) 0x408, 0x508, 0x608, 0x708,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) 0x808, 0x908, 0xa08, 0xb08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) /* Number of ways a tad entry is interleaved. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) static const u32 knl_tad_ways[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) 8, 6, 4, 3, 2, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) * Retrieve the n'th Target Address Decode table entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) * from the memory controller's TAD table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) * @pvt: driver private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) * @entry: which entry you want to retrieve
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) * @mc: which memory controller (0 or 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) * @offset: output tad range offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) * @limit: output address of first byte above tad range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) * @ways: output number of interleave ways
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) * The offset value has curious semantics. It's a sort of running total
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) * of the sizes of all the memory regions that aren't mapped in this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) * tad table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) static int knl_get_tad(const struct sbridge_pvt *pvt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) const int entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) const int mc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) u64 *offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) u64 *limit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) int *ways)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) u32 reg_limit_lo, reg_offset_lo, reg_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) struct pci_dev *pci_mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) int way_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) switch (mc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) pci_mc = pvt->knl.pci_mc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) pci_mc = pvt->knl.pci_mc1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) pci_read_config_dword(pci_mc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) knl_tad_dram_limit_lo[entry], ®_limit_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) pci_read_config_dword(pci_mc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) knl_tad_dram_offset_lo[entry], ®_offset_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) pci_read_config_dword(pci_mc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) knl_tad_dram_hi[entry], ®_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) /* Is this TAD entry enabled? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) if (!GET_BITFIELD(reg_limit_lo, 0, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) way_id = GET_BITFIELD(reg_limit_lo, 3, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) if (way_id < ARRAY_SIZE(knl_tad_ways)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) *ways = knl_tad_ways[way_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) *ways = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) sbridge_printk(KERN_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) "Unexpected value %d in mc_tad_limit_lo wayness field\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) way_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) * The least significant 6 bits of base and limit are truncated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) * For limit, we fill the missing bits with 1s.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) *offset = ((u64) GET_BITFIELD(reg_offset_lo, 6, 31) << 6) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) ((u64) GET_BITFIELD(reg_hi, 0, 15) << 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) *limit = ((u64) GET_BITFIELD(reg_limit_lo, 6, 31) << 6) | 63 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) ((u64) GET_BITFIELD(reg_hi, 16, 31) << 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) /* Determine which memory controller is responsible for a given channel. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) static int knl_channel_mc(int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) WARN_ON(channel < 0 || channel >= 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) return channel < 3 ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) * Get the Nth entry from EDC_ROUTE_TABLE register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) * (This is the per-tile mapping of logical interleave targets to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) * physical EDC modules.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) * entry 0: 0:2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) * 1: 3:5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) * 2: 6:8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) * 3: 9:11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) * 4: 12:14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) * 5: 15:17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) * 6: 18:20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) * 7: 21:23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) * reserved: 24:31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) static u32 knl_get_edc_route(int entry, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) WARN_ON(entry >= KNL_MAX_EDCS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) return GET_BITFIELD(reg, entry*3, (entry*3)+2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) * Get the Nth entry from MC_ROUTE_TABLE register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) * (This is the per-tile mapping of logical interleave targets to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) * physical DRAM channels modules.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) * entry 0: mc 0:2 channel 18:19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) * 1: mc 3:5 channel 20:21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) * 2: mc 6:8 channel 22:23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) * 3: mc 9:11 channel 24:25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) * 4: mc 12:14 channel 26:27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) * 5: mc 15:17 channel 28:29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) * reserved: 30:31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) * Though we have 3 bits to identify the MC, we should only see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) * the values 0 or 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) static u32 knl_get_mc_route(int entry, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) int mc, chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) WARN_ON(entry >= KNL_MAX_CHANNELS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) mc = GET_BITFIELD(reg, entry*3, (entry*3)+2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) chan = GET_BITFIELD(reg, (entry*2) + 18, (entry*2) + 18 + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) return knl_channel_remap(mc, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) * Render the EDC_ROUTE register in human-readable form.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) * Output string s should be at least KNL_MAX_EDCS*2 bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) static void knl_show_edc_route(u32 reg, char *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) for (i = 0; i < KNL_MAX_EDCS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) s[i*2] = knl_get_edc_route(i, reg) + '0';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) s[i*2+1] = '-';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) s[KNL_MAX_EDCS*2 - 1] = '\0';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) * Render the MC_ROUTE register in human-readable form.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) * Output string s should be at least KNL_MAX_CHANNELS*2 bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) static void knl_show_mc_route(u32 reg, char *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) for (i = 0; i < KNL_MAX_CHANNELS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) s[i*2] = knl_get_mc_route(i, reg) + '0';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) s[i*2+1] = '-';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) s[KNL_MAX_CHANNELS*2 - 1] = '\0';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) #define KNL_EDC_ROUTE 0xb8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) #define KNL_MC_ROUTE 0xb4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) /* Is this dram rule backed by regular DRAM in flat mode? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) #define KNL_EDRAM(reg) GET_BITFIELD(reg, 29, 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) /* Is this dram rule cached? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) #define KNL_CACHEABLE(reg) GET_BITFIELD(reg, 28, 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) /* Is this rule backed by edc ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) #define KNL_EDRAM_ONLY(reg) GET_BITFIELD(reg, 29, 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) /* Is this rule backed by DRAM, cacheable in EDRAM? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) #define KNL_CACHEABLE(reg) GET_BITFIELD(reg, 28, 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) /* Is this rule mod3? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) #define KNL_MOD3(reg) GET_BITFIELD(reg, 27, 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) * Figure out how big our RAM modules are.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) * The DIMMMTR register in KNL doesn't tell us the size of the DIMMs, so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) * have to figure this out from the SAD rules, interleave lists, route tables,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) * and TAD rules.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) * SAD rules can have holes in them (e.g. the 3G-4G hole), so we have to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) * inspect the TAD rules to figure out how large the SAD regions really are.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) * When we know the real size of a SAD region and how many ways it's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) * interleaved, we know the individual contribution of each channel to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) * TAD is size/ways.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) * Finally, we have to check whether each channel participates in each SAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) * region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) * Fortunately, KNL only supports one DIMM per channel, so once we know how
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) * much memory the channel uses, we know the DIMM is at least that large.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) * (The BIOS might possibly choose not to map all available memory, in which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) * case we will underreport the size of the DIMM.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) * In theory, we could try to determine the EDC sizes as well, but that would
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) * only work in flat mode, not in cache mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) * @mc_sizes: Output sizes of channels (must have space for KNL_MAX_CHANNELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) * elements)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) static int knl_get_dimm_capacity(struct sbridge_pvt *pvt, u64 *mc_sizes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) u64 sad_base, sad_limit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) u64 tad_base, tad_size, tad_limit, tad_deadspace, tad_livespace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) int sad_rule = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) int tad_rule = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) int intrlv_ways, tad_ways;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) u32 first_pkg, pkg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) u64 sad_actual_size[2]; /* sad size accounting for holes, per mc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) u32 dram_rule, interleave_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) u32 mc_route_reg[KNL_MAX_CHAS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) u32 edc_route_reg[KNL_MAX_CHAS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) int edram_only;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) char edc_route_string[KNL_MAX_EDCS*2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) char mc_route_string[KNL_MAX_CHANNELS*2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) int cur_reg_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) int mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) int channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) int participants[KNL_MAX_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) for (i = 0; i < KNL_MAX_CHANNELS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) mc_sizes[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) /* Read the EDC route table in each CHA. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) cur_reg_start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) for (i = 0; i < KNL_MAX_CHAS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) pci_read_config_dword(pvt->knl.pci_cha[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) KNL_EDC_ROUTE, &edc_route_reg[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) if (i > 0 && edc_route_reg[i] != edc_route_reg[i-1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) knl_show_edc_route(edc_route_reg[i-1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) edc_route_string);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) if (cur_reg_start == i-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) edac_dbg(0, "edc route table for CHA %d: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) cur_reg_start, edc_route_string);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) edac_dbg(0, "edc route table for CHA %d-%d: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) cur_reg_start, i-1, edc_route_string);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) cur_reg_start = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) knl_show_edc_route(edc_route_reg[i-1], edc_route_string);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) if (cur_reg_start == i-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) edac_dbg(0, "edc route table for CHA %d: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) cur_reg_start, edc_route_string);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) edac_dbg(0, "edc route table for CHA %d-%d: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) cur_reg_start, i-1, edc_route_string);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) /* Read the MC route table in each CHA. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) cur_reg_start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) for (i = 0; i < KNL_MAX_CHAS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) pci_read_config_dword(pvt->knl.pci_cha[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) KNL_MC_ROUTE, &mc_route_reg[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) if (i > 0 && mc_route_reg[i] != mc_route_reg[i-1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) knl_show_mc_route(mc_route_reg[i-1], mc_route_string);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) if (cur_reg_start == i-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) edac_dbg(0, "mc route table for CHA %d: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) cur_reg_start, mc_route_string);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) edac_dbg(0, "mc route table for CHA %d-%d: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) cur_reg_start, i-1, mc_route_string);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) cur_reg_start = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) knl_show_mc_route(mc_route_reg[i-1], mc_route_string);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) if (cur_reg_start == i-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) edac_dbg(0, "mc route table for CHA %d: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) cur_reg_start, mc_route_string);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) edac_dbg(0, "mc route table for CHA %d-%d: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) cur_reg_start, i-1, mc_route_string);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) /* Process DRAM rules */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) for (sad_rule = 0; sad_rule < pvt->info.max_sad; sad_rule++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) /* previous limit becomes the new base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) sad_base = sad_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) pci_read_config_dword(pvt->pci_sad0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) pvt->info.dram_rule[sad_rule], &dram_rule);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) if (!DRAM_RULE_ENABLE(dram_rule))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) edram_only = KNL_EDRAM_ONLY(dram_rule);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) sad_limit = pvt->info.sad_limit(dram_rule)+1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) pci_read_config_dword(pvt->pci_sad0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) pvt->info.interleave_list[sad_rule], &interleave_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) * Find out how many ways this dram rule is interleaved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) * We stop when we see the first channel again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) first_pkg = sad_pkg(pvt->info.interleave_pkg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) interleave_reg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) for (intrlv_ways = 1; intrlv_ways < 8; intrlv_ways++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) pkg = sad_pkg(pvt->info.interleave_pkg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) interleave_reg, intrlv_ways);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) if ((pkg & 0x8) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) * 0 bit means memory is non-local,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) * which KNL doesn't support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) edac_dbg(0, "Unexpected interleave target %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) pkg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) if (pkg == first_pkg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) if (KNL_MOD3(dram_rule))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) intrlv_ways *= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) edac_dbg(3, "dram rule %d (base 0x%llx, limit 0x%llx), %d way interleave%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) sad_rule,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) sad_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) sad_limit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) intrlv_ways,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) edram_only ? ", EDRAM" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) * Find out how big the SAD region really is by iterating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) * over TAD tables (SAD regions may contain holes).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) * Each memory controller might have a different TAD table, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) * we have to look at both.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) * Livespace is the memory that's mapped in this TAD table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) * deadspace is the holes (this could be the MMIO hole, or it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) * could be memory that's mapped by the other TAD table but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) * not this one).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) for (mc = 0; mc < 2; mc++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) sad_actual_size[mc] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) tad_livespace = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) for (tad_rule = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) tad_rule < ARRAY_SIZE(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) knl_tad_dram_limit_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) tad_rule++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) if (knl_get_tad(pvt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) tad_rule,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) mc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) &tad_deadspace,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) &tad_limit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) &tad_ways))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) tad_size = (tad_limit+1) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) (tad_livespace + tad_deadspace);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) tad_livespace += tad_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) tad_base = (tad_limit+1) - tad_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) if (tad_base < sad_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) if (tad_limit > sad_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) edac_dbg(0, "TAD region overlaps lower SAD boundary -- TAD tables may be configured incorrectly.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) } else if (tad_base < sad_limit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) if (tad_limit+1 > sad_limit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) edac_dbg(0, "TAD region overlaps upper SAD boundary -- TAD tables may be configured incorrectly.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) /* TAD region is completely inside SAD region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) edac_dbg(3, "TAD region %d 0x%llx - 0x%llx (%lld bytes) table%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) tad_rule, tad_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) tad_limit, tad_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) mc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) sad_actual_size[mc] += tad_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) for (mc = 0; mc < 2; mc++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) edac_dbg(3, " total TAD DRAM footprint in table%d : 0x%llx (%lld bytes)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) mc, sad_actual_size[mc], sad_actual_size[mc]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) /* Ignore EDRAM rule */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) if (edram_only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) /* Figure out which channels participate in interleave. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) for (channel = 0; channel < KNL_MAX_CHANNELS; channel++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) participants[channel] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) /* For each channel, does at least one CHA have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) * this channel mapped to the given target?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) for (channel = 0; channel < KNL_MAX_CHANNELS; channel++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) int target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) int cha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) for (target = 0; target < KNL_MAX_CHANNELS; target++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) for (cha = 0; cha < KNL_MAX_CHAS; cha++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) if (knl_get_mc_route(target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) mc_route_reg[cha]) == channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) && !participants[channel]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) participants[channel] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) for (channel = 0; channel < KNL_MAX_CHANNELS; channel++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) mc = knl_channel_mc(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) if (participants[channel]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) edac_dbg(4, "mc channel %d contributes %lld bytes via sad entry %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) sad_actual_size[mc]/intrlv_ways,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) sad_rule);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) mc_sizes[channel] +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) sad_actual_size[mc]/intrlv_ways;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) static void get_source_id(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) struct sbridge_pvt *pvt = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) pvt->info.type == KNIGHTS_LANDING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) pci_read_config_dword(pvt->pci_br0, SAD_TARGET, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) if (pvt->info.type == KNIGHTS_LANDING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) pvt->sbridge_dev->source_id = SOURCE_ID_KNL(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) pvt->sbridge_dev->source_id = SOURCE_ID(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) static int __populate_dimms(struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) u64 knl_mc_sizes[KNL_MAX_CHANNELS],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) enum edac_type mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) struct sbridge_pvt *pvt = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) int channels = pvt->info.type == KNIGHTS_LANDING ? KNL_MAX_CHANNELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) : NUM_CHANNELS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) unsigned int i, j, banks, ranks, rows, cols, npages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) struct dimm_info *dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) enum mem_type mtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) u64 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) mtype = pvt->info.get_memory_type(pvt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) if (mtype == MEM_RDDR3 || mtype == MEM_RDDR4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) edac_dbg(0, "Memory is registered\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) else if (mtype == MEM_UNKNOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) edac_dbg(0, "Cannot determine memory type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) edac_dbg(0, "Memory is unregistered\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) if (mtype == MEM_DDR4 || mtype == MEM_RDDR4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) banks = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) banks = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) for (i = 0; i < channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) u32 mtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) int max_dimms_per_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) if (pvt->info.type == KNIGHTS_LANDING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) max_dimms_per_channel = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) if (!pvt->knl.pci_channel[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) max_dimms_per_channel = ARRAY_SIZE(mtr_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) if (!pvt->pci_tad[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) for (j = 0; j < max_dimms_per_channel; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) dimm = edac_get_dimm(mci, i, j, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) if (pvt->info.type == KNIGHTS_LANDING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) pci_read_config_dword(pvt->knl.pci_channel[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) knl_mtr_reg, &mtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) pci_read_config_dword(pvt->pci_tad[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) mtr_regs[j], &mtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) edac_dbg(4, "Channel #%d MTR%d = %x\n", i, j, mtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) if (IS_DIMM_PRESENT(mtr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) if (!IS_ECC_ENABLED(pvt->info.mcmtr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) sbridge_printk(KERN_ERR, "CPU SrcID #%d, Ha #%d, Channel #%d has DIMMs, but ECC is disabled\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) pvt->sbridge_dev->source_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) pvt->sbridge_dev->dom, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) pvt->channel[i].dimms++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) ranks = numrank(pvt->info.type, mtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) if (pvt->info.type == KNIGHTS_LANDING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) /* For DDR4, this is fixed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) cols = 1 << 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) rows = knl_mc_sizes[i] /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) ((u64) cols * ranks * banks * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) rows = numrow(mtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) cols = numcol(mtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) size = ((u64)rows * cols * banks * ranks) >> (20 - 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) npages = MiB_TO_PAGES(size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) edac_dbg(0, "mc#%d: ha %d channel %d, dimm %d, %lld MiB (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) pvt->sbridge_dev->mc, pvt->sbridge_dev->dom, i, j,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) size, npages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) banks, ranks, rows, cols);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) dimm->nr_pages = npages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) dimm->grain = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) dimm->dtype = pvt->info.get_width(pvt, mtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) dimm->mtype = mtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) dimm->edac_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) snprintf(dimm->label, sizeof(dimm->label),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) "CPU_SrcID#%u_Ha#%u_Chan#%u_DIMM#%u",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom, i, j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) static int get_dimm_config(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) struct sbridge_pvt *pvt = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) u64 knl_mc_sizes[KNL_MAX_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) enum edac_type mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) pvt->sbridge_dev->node_id = pvt->info.get_node_id(pvt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) edac_dbg(0, "mc#%d: Node ID: %d, source ID: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) pvt->sbridge_dev->mc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) pvt->sbridge_dev->node_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) pvt->sbridge_dev->source_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) /* KNL doesn't support mirroring or lockstep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) * and is always closed page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) if (pvt->info.type == KNIGHTS_LANDING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) mode = EDAC_S4ECD4ED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) pvt->mirror_mode = NON_MIRRORING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) pvt->is_cur_addr_mirrored = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) if (knl_get_dimm_capacity(pvt, knl_mc_sizes) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) if (pci_read_config_dword(pvt->pci_ta, KNL_MCMTR, &pvt->info.mcmtr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) edac_dbg(0, "Failed to read KNL_MCMTR register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) if (pci_read_config_dword(pvt->pci_ha, HASWELL_HASYSDEFEATURE2, ®)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) edac_dbg(0, "Failed to read HASWELL_HASYSDEFEATURE2 register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) pvt->is_chan_hash = GET_BITFIELD(reg, 21, 21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) if (GET_BITFIELD(reg, 28, 28)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) pvt->mirror_mode = ADDR_RANGE_MIRRORING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) edac_dbg(0, "Address range partial memory mirroring is enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) goto next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) if (pci_read_config_dword(pvt->pci_ras, RASENABLES, ®)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) edac_dbg(0, "Failed to read RASENABLES register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) if (IS_MIRROR_ENABLED(reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) pvt->mirror_mode = FULL_MIRRORING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) edac_dbg(0, "Full memory mirroring is enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) pvt->mirror_mode = NON_MIRRORING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) edac_dbg(0, "Memory mirroring is disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) next:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) if (pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) edac_dbg(0, "Failed to read MCMTR register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) edac_dbg(0, "Lockstep is enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) mode = EDAC_S8ECD8ED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) pvt->is_lockstep = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) edac_dbg(0, "Lockstep is disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) mode = EDAC_S4ECD4ED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) pvt->is_lockstep = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) if (IS_CLOSE_PG(pvt->info.mcmtr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) edac_dbg(0, "address map is on closed page mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) pvt->is_close_pg = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) edac_dbg(0, "address map is on open page mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) pvt->is_close_pg = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) return __populate_dimms(mci, knl_mc_sizes, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) static void get_memory_layout(const struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) struct sbridge_pvt *pvt = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) int i, j, k, n_sads, n_tads, sad_interl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) u64 limit, prv = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) u64 tmp_mb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) u32 gb, mb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) u32 rir_way;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) * Step 1) Get TOLM/TOHM ranges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) pvt->tolm = pvt->info.get_tolm(pvt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) tmp_mb = (1 + pvt->tolm) >> 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) gb = div_u64_rem(tmp_mb, 1024, &mb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) edac_dbg(0, "TOLM: %u.%03u GB (0x%016Lx)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) gb, (mb*1000)/1024, (u64)pvt->tolm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) /* Address range is already 45:25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) pvt->tohm = pvt->info.get_tohm(pvt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) tmp_mb = (1 + pvt->tohm) >> 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) gb = div_u64_rem(tmp_mb, 1024, &mb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) edac_dbg(0, "TOHM: %u.%03u GB (0x%016Lx)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) gb, (mb*1000)/1024, (u64)pvt->tohm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) * Step 2) Get SAD range and SAD Interleave list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) * TAD registers contain the interleave wayness. However, it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) * seems simpler to just discover it indirectly, with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) * algorithm bellow.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) prv = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) /* SAD_LIMIT Address range is 45:26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) limit = pvt->info.sad_limit(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) if (!DRAM_RULE_ENABLE(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) if (limit <= prv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) tmp_mb = (limit + 1) >> 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) gb = div_u64_rem(tmp_mb, 1024, &mb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) edac_dbg(0, "SAD#%d %s up to %u.%03u GB (0x%016Lx) Interleave: %s reg=0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) n_sads,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) show_dram_attr(pvt->info.dram_attr(reg)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) gb, (mb*1000)/1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) ((u64)tmp_mb) << 20L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) get_intlv_mode_str(reg, pvt->info.type),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) prv = limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) for (j = 0; j < 8; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) if (j > 0 && sad_interl == pkg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) edac_dbg(0, "SAD#%d, interleave #%d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) n_sads, j, pkg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) if (pvt->info.type == KNIGHTS_LANDING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) * Step 3) Get TAD range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) prv = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) pci_read_config_dword(pvt->pci_ha, tad_dram_rule[n_tads], ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) limit = TAD_LIMIT(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) if (limit <= prv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) tmp_mb = (limit + 1) >> 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) gb = div_u64_rem(tmp_mb, 1024, &mb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) n_tads, gb, (mb*1000)/1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) ((u64)tmp_mb) << 20L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) (u32)(1 << TAD_SOCK(reg)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) (u32)TAD_CH(reg) + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) (u32)TAD_TGT0(reg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) (u32)TAD_TGT1(reg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) (u32)TAD_TGT2(reg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) (u32)TAD_TGT3(reg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) prv = limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) * Step 4) Get TAD offsets, per each channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) for (i = 0; i < NUM_CHANNELS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) if (!pvt->channel[i].dimms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) for (j = 0; j < n_tads; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) pci_read_config_dword(pvt->pci_tad[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) tad_ch_nilv_offset[j],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) tmp_mb = TAD_OFFSET(reg) >> 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) gb = div_u64_rem(tmp_mb, 1024, &mb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) edac_dbg(0, "TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) i, j,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) gb, (mb*1000)/1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) ((u64)tmp_mb) << 20L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) * Step 6) Get RIR Wayness/Limit, per each channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) for (i = 0; i < NUM_CHANNELS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) if (!pvt->channel[i].dimms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) for (j = 0; j < MAX_RIR_RANGES; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) pci_read_config_dword(pvt->pci_tad[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) rir_way_limit[j],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) if (!IS_RIR_VALID(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) tmp_mb = pvt->info.rir_limit(reg) >> 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) rir_way = 1 << RIR_WAY(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) gb = div_u64_rem(tmp_mb, 1024, &mb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) edac_dbg(0, "CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) i, j,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) gb, (mb*1000)/1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) ((u64)tmp_mb) << 20L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) rir_way,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) for (k = 0; k < rir_way; k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) pci_read_config_dword(pvt->pci_tad[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) rir_offset[j][k],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) tmp_mb = RIR_OFFSET(pvt->info.type, reg) << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) gb = div_u64_rem(tmp_mb, 1024, &mb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) edac_dbg(0, "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) i, j, k,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) gb, (mb*1000)/1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) ((u64)tmp_mb) << 20L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) (u32)RIR_RNK_TGT(pvt->info.type, reg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) static struct mem_ctl_info *get_mci_for_node_id(u8 node_id, u8 ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) struct sbridge_dev *sbridge_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) if (sbridge_dev->node_id == node_id && sbridge_dev->dom == ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) return sbridge_dev->mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) static int get_memory_error_data(struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) u64 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) u8 *socket, u8 *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) long *channel_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) u8 *rank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) char **area_type, char *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) struct mem_ctl_info *new_mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) struct sbridge_pvt *pvt = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) struct pci_dev *pci_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) int n_rir, n_sads, n_tads, sad_way, sck_xch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) int sad_interl, idx, base_ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) int interleave_mode, shiftup = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) unsigned int sad_interleave[MAX_INTERLEAVE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) u32 reg, dram_rule;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) u8 ch_way, sck_way, pkg, sad_ha = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) u32 tad_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) u32 rir_way;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) u32 mb, gb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) u64 ch_addr, offset, limit = 0, prv = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) * Step 0) Check if the address is at special memory ranges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) * The check bellow is probably enough to fill all cases where
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) * the error is not inside a memory, except for the legacy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) * range (e. g. VGA addresses). It is unlikely, however, that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) * memory controller would generate an error on that range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) sprintf(msg, "Error at TOLM area, on addr 0x%08Lx", addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) if (addr >= (u64)pvt->tohm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) sprintf(msg, "Error at MMIOH area, on addr 0x%016Lx", addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) * Step 1) Get socket
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) if (!DRAM_RULE_ENABLE(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) limit = pvt->info.sad_limit(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) if (limit <= prv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) sprintf(msg, "Can't discover the memory socket");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) if (addr <= limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) prv = limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) if (n_sads == pvt->info.max_sad) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) sprintf(msg, "Can't discover the memory socket");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) dram_rule = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) *area_type = show_dram_attr(pvt->info.dram_attr(dram_rule));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) interleave_mode = pvt->info.interleave_mode(dram_rule);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) if (pvt->info.type == SANDY_BRIDGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) for (sad_way = 0; sad_way < 8; sad_way++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) if (sad_way > 0 && sad_interl == pkg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) sad_interleave[sad_way] = pkg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) edac_dbg(0, "SAD interleave #%d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) sad_way, sad_interleave[sad_way]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) edac_dbg(0, "mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) pvt->sbridge_dev->mc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) n_sads,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) limit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) sad_way + 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) !interleave_mode ? "" : "XOR[18:16]");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) if (interleave_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) idx = ((addr >> 6) ^ (addr >> 16)) & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) idx = (addr >> 6) & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) switch (sad_way) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) idx = idx & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) idx = idx & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) sprintf(msg, "Can't discover socket interleave");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) *socket = sad_interleave[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) idx, sad_way, *socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) } else if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) int bits, a7mode = A7MODE(dram_rule);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) if (a7mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) /* A7 mode swaps P9 with P6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) bits = GET_BITFIELD(addr, 7, 8) << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) bits |= GET_BITFIELD(addr, 9, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) bits = GET_BITFIELD(addr, 6, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) if (interleave_mode == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) /* interleave mode will XOR {8,7,6} with {18,17,16} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) idx = GET_BITFIELD(addr, 16, 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) idx ^= bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) idx = bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) *socket = sad_pkg_socket(pkg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) sad_ha = sad_pkg_ha(pkg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) if (a7mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) /* MCChanShiftUpEnable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) pci_read_config_dword(pvt->pci_ha, HASWELL_HASYSDEFEATURE2, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) shiftup = GET_BITFIELD(reg, 22, 22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %i, shiftup: %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) idx, *socket, sad_ha, shiftup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) /* Ivy Bridge's SAD mode doesn't support XOR interleave mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) idx = (addr >> 6) & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) *socket = sad_pkg_socket(pkg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) sad_ha = sad_pkg_ha(pkg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) idx, *socket, sad_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) *ha = sad_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) * Move to the proper node structure, in order to access the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) * right PCI registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) new_mci = get_mci_for_node_id(*socket, sad_ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) if (!new_mci) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) sprintf(msg, "Struct for socket #%u wasn't initialized",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) *socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) mci = new_mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) pvt = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) * Step 2) Get memory channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) prv = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) pci_ha = pvt->pci_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) pci_read_config_dword(pci_ha, tad_dram_rule[n_tads], ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) limit = TAD_LIMIT(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) if (limit <= prv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) sprintf(msg, "Can't discover the memory channel");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) if (addr <= limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) prv = limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) if (n_tads == MAX_TAD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) sprintf(msg, "Can't discover the memory channel");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) ch_way = TAD_CH(reg) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) sck_way = TAD_SOCK(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) if (ch_way == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) idx = addr >> 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) idx = (addr >> (6 + sck_way + shiftup)) & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) if (pvt->is_chan_hash)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) idx = haswell_chan_hash(idx, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) idx = idx % ch_way;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) * FIXME: Shouldn't we use CHN_IDX_OFFSET() here, when ch_way == 3 ???
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) switch (idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) base_ch = TAD_TGT0(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) base_ch = TAD_TGT1(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) base_ch = TAD_TGT2(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) base_ch = TAD_TGT3(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) sprintf(msg, "Can't discover the TAD target");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) *channel_mask = 1 << base_ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) pci_read_config_dword(pvt->pci_tad[base_ch], tad_ch_nilv_offset[n_tads], &tad_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) if (pvt->mirror_mode == FULL_MIRRORING ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) (pvt->mirror_mode == ADDR_RANGE_MIRRORING && n_tads == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) *channel_mask |= 1 << ((base_ch + 2) % 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) switch(ch_way) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) sck_xch = (1 << sck_way) * (ch_way >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) sprintf(msg, "Invalid mirror set. Can't decode addr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) pvt->is_cur_addr_mirrored = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) sck_xch = (1 << sck_way) * ch_way;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) pvt->is_cur_addr_mirrored = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) if (pvt->is_lockstep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) *channel_mask |= 1 << ((base_ch + 1) % 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) offset = TAD_OFFSET(tad_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) edac_dbg(0, "TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) n_tads,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) limit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) sck_way,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) ch_way,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) base_ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) *channel_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) /* Calculate channel address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) /* Remove the TAD offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) if (offset > addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) sprintf(msg, "Can't calculate ch addr: TAD offset 0x%08Lx is too high for addr 0x%08Lx!",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) offset, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) ch_addr = addr - offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) ch_addr >>= (6 + shiftup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) ch_addr /= sck_xch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) ch_addr <<= (6 + shiftup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) ch_addr |= addr & ((1 << (6 + shiftup)) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) * Step 3) Decode rank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) for (n_rir = 0; n_rir < MAX_RIR_RANGES; n_rir++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) pci_read_config_dword(pvt->pci_tad[base_ch], rir_way_limit[n_rir], ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) if (!IS_RIR_VALID(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) limit = pvt->info.rir_limit(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) gb = div_u64_rem(limit >> 20, 1024, &mb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) edac_dbg(0, "RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) n_rir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) gb, (mb*1000)/1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) limit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) 1 << RIR_WAY(reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) if (ch_addr <= limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) if (n_rir == MAX_RIR_RANGES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) sprintf(msg, "Can't discover the memory rank for ch addr 0x%08Lx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) ch_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) rir_way = RIR_WAY(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) if (pvt->is_close_pg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) idx = (ch_addr >> 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) idx = (ch_addr >> 13); /* FIXME: Datasheet says to shift by 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) idx %= 1 << rir_way;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) pci_read_config_dword(pvt->pci_tad[base_ch], rir_offset[n_rir][idx], ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) *rank = RIR_RNK_TGT(pvt->info.type, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) n_rir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) ch_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) limit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) rir_way,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) static int get_memory_error_data_from_mce(struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) const struct mce *m, u8 *socket,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) u8 *ha, long *channel_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) char *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) u32 reg, channel = GET_BITFIELD(m->status, 0, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) struct mem_ctl_info *new_mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) struct sbridge_pvt *pvt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) struct pci_dev *pci_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) bool tad0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) if (channel >= NUM_CHANNELS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) sprintf(msg, "Invalid channel 0x%x", channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) pvt = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) if (!pvt->info.get_ha) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) sprintf(msg, "No get_ha()");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) *ha = pvt->info.get_ha(m->bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) if (*ha != 0 && *ha != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) sprintf(msg, "Impossible bank %d", m->bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) *socket = m->socketid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) new_mci = get_mci_for_node_id(*socket, *ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) if (!new_mci) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) strcpy(msg, "mci socket got corrupted!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) pvt = new_mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) pci_ha = pvt->pci_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) pci_read_config_dword(pci_ha, tad_dram_rule[0], ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) tad0 = m->addr <= TAD_LIMIT(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) *channel_mask = 1 << channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) if (pvt->mirror_mode == FULL_MIRRORING ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) (pvt->mirror_mode == ADDR_RANGE_MIRRORING && tad0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) *channel_mask |= 1 << ((channel + 2) % 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) pvt->is_cur_addr_mirrored = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) pvt->is_cur_addr_mirrored = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) if (pvt->is_lockstep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) *channel_mask |= 1 << ((channel + 1) % 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) Device initialization routines: put/get, init/exit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) * sbridge_put_all_devices 'put' all the devices that we have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) * reserved via 'get'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) static void sbridge_put_devices(struct sbridge_dev *sbridge_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) edac_dbg(0, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) for (i = 0; i < sbridge_dev->n_devs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) struct pci_dev *pdev = sbridge_dev->pdev[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) if (!pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) edac_dbg(0, "Removing dev %02x:%02x.%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) pdev->bus->number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) pci_dev_put(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) static void sbridge_put_all_devices(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) struct sbridge_dev *sbridge_dev, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) list_for_each_entry_safe(sbridge_dev, tmp, &sbridge_edac_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) sbridge_put_devices(sbridge_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) free_sbridge_dev(sbridge_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) static int sbridge_get_onedevice(struct pci_dev **prev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) u8 *num_mc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) const struct pci_id_table *table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) const unsigned devno,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) const int multi_bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) struct sbridge_dev *sbridge_dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) const struct pci_id_descr *dev_descr = &table->descr[devno];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) struct pci_dev *pdev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) int seg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) u8 bus = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) sbridge_printk(KERN_DEBUG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) "Seeking for: PCI ID %04x:%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) dev_descr->dev_id, *prev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) if (!pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) if (*prev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) *prev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) if (dev_descr->optional)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) /* if the HA wasn't found */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) if (devno == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) sbridge_printk(KERN_INFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) "Device not found: %04x:%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) /* End of list, leave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) seg = pci_domain_nr(pdev->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) bus = pdev->bus->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) next_imc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) sbridge_dev = get_sbridge_dev(seg, bus, dev_descr->dom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) multi_bus, sbridge_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) if (!sbridge_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) /* If the HA1 wasn't found, don't create EDAC second memory controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) if (dev_descr->dom == IMC1 && devno != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) edac_dbg(0, "Skip IMC1: %04x:%04x (since HA1 was absent)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) pci_dev_put(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) if (dev_descr->dom == SOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) goto out_imc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) sbridge_dev = alloc_sbridge_dev(seg, bus, dev_descr->dom, table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) if (!sbridge_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) pci_dev_put(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) (*num_mc)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) if (sbridge_dev->pdev[sbridge_dev->i_devs]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) sbridge_printk(KERN_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) "Duplicated device for %04x:%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) pci_dev_put(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) sbridge_dev->pdev[sbridge_dev->i_devs++] = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) /* pdev belongs to more than one IMC, do extra gets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) if (++i > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) pci_dev_get(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) if (dev_descr->dom == SOCK && i < table->n_imcs_per_sock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) goto next_imc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) out_imc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) /* Be sure that the device is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) if (unlikely(pci_enable_device(pdev) < 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) sbridge_printk(KERN_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) "Couldn't enable %04x:%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) edac_dbg(0, "Detected %04x:%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) * As stated on drivers/pci/search.c, the reference count for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) * @from is always decremented if it is not %NULL. So, as we need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) * to get all devices up to null, we need to do a get for the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) pci_dev_get(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) *prev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) * sbridge_get_all_devices - Find and perform 'get' operation on the MCH's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) * devices we want to reference for this driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) * @num_mc: pointer to the memory controllers count, to be incremented in case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) * of success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) * @table: model specific table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) * returns 0 in case of success or error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) static int sbridge_get_all_devices(u8 *num_mc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) const struct pci_id_table *table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) int i, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) struct pci_dev *pdev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) int allow_dups = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) int multi_bus = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) if (table->type == KNIGHTS_LANDING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) allow_dups = multi_bus = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) while (table && table->descr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) for (i = 0; i < table->n_devs_per_sock; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) if (!allow_dups || i == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) table->descr[i].dev_id !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) table->descr[i-1].dev_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) pdev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) rc = sbridge_get_onedevice(&pdev, num_mc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) table, i, multi_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) if (i == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) i = table->n_devs_per_sock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) sbridge_put_all_devices();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) } while (pdev && !allow_dups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) table++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) * Device IDs for {SBRIDGE,IBRIDGE,HASWELL,BROADWELL}_IMC_HA0_TAD0 are in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) * the format: XXXa. So we can convert from a device to the corresponding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) * channel like this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) #define TAD_DEV_TO_CHAN(dev) (((dev) & 0xf) - 0xa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) static int sbridge_mci_bind_devs(struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) struct sbridge_dev *sbridge_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) struct sbridge_pvt *pvt = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) u8 saw_chan_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) for (i = 0; i < sbridge_dev->n_devs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) pdev = sbridge_dev->pdev[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) if (!pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) switch (pdev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) pvt->pci_sad0 = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) pvt->pci_sad1 = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) case PCI_DEVICE_ID_INTEL_SBRIDGE_BR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) pvt->pci_br0 = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) pvt->pci_ha = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) pvt->pci_ta = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) pvt->pci_ras = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) int id = TAD_DEV_TO_CHAN(pdev->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) pvt->pci_tad[id] = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) saw_chan_mask |= 1 << id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) pvt->pci_ddrio = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) edac_dbg(0, "Associated PCI %02x:%02x, bus %d with dev = %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) pdev->vendor, pdev->device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) sbridge_dev->bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) /* Check if everything were registered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) !pvt->pci_ras || !pvt->pci_ta)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) goto enodev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) if (saw_chan_mask != 0x0f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) goto enodev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) enodev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) sbridge_printk(KERN_ERR, "Unexpected device %02x:%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) PCI_VENDOR_ID_INTEL, pdev->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) static int ibridge_mci_bind_devs(struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) struct sbridge_dev *sbridge_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) struct sbridge_pvt *pvt = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) u8 saw_chan_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) for (i = 0; i < sbridge_dev->n_devs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) pdev = sbridge_dev->pdev[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) if (!pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) switch (pdev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) pvt->pci_ha = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) pvt->pci_ta = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) pvt->pci_ras = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) int id = TAD_DEV_TO_CHAN(pdev->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) pvt->pci_tad[id] = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) saw_chan_mask |= 1 << id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) pvt->pci_ddrio = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) pvt->pci_ddrio = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) case PCI_DEVICE_ID_INTEL_IBRIDGE_SAD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) pvt->pci_sad0 = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) case PCI_DEVICE_ID_INTEL_IBRIDGE_BR0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) pvt->pci_br0 = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) case PCI_DEVICE_ID_INTEL_IBRIDGE_BR1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) pvt->pci_br1 = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) sbridge_dev->bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) /* Check if everything were registered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_br0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) !pvt->pci_br1 || !pvt->pci_ras || !pvt->pci_ta)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) goto enodev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) if (saw_chan_mask != 0x0f && /* -EN/-EX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) saw_chan_mask != 0x03) /* -EP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) goto enodev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) enodev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) sbridge_printk(KERN_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) "Unexpected device %02x:%02x\n", PCI_VENDOR_ID_INTEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) pdev->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) static int haswell_mci_bind_devs(struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) struct sbridge_dev *sbridge_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) struct sbridge_pvt *pvt = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) u8 saw_chan_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) /* there's only one device per system; not tied to any bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) if (pvt->info.pci_vtd == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) /* result will be checked later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) for (i = 0; i < sbridge_dev->n_devs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) pdev = sbridge_dev->pdev[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) if (!pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) switch (pdev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) pvt->pci_sad0 = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) pvt->pci_sad1 = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) pvt->pci_ha = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) pvt->pci_ta = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) pvt->pci_ras = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) int id = TAD_DEV_TO_CHAN(pdev->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) pvt->pci_tad[id] = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) saw_chan_mask |= 1 << id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) if (!pvt->pci_ddrio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) pvt->pci_ddrio = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) sbridge_dev->bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) /* Check if everything were registered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_sad1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) goto enodev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) if (saw_chan_mask != 0x0f && /* -EN/-EX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) saw_chan_mask != 0x03) /* -EP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) goto enodev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) enodev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) static int broadwell_mci_bind_devs(struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) struct sbridge_dev *sbridge_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) struct sbridge_pvt *pvt = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) u8 saw_chan_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) /* there's only one device per system; not tied to any bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) if (pvt->info.pci_vtd == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) /* result will be checked later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) for (i = 0; i < sbridge_dev->n_devs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) pdev = sbridge_dev->pdev[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) if (!pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) switch (pdev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) pvt->pci_sad0 = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) pvt->pci_sad1 = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) pvt->pci_ha = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) pvt->pci_ta = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) pvt->pci_ras = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) int id = TAD_DEV_TO_CHAN(pdev->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) pvt->pci_tad[id] = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) saw_chan_mask |= 1 << id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) pvt->pci_ddrio = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) sbridge_dev->bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) /* Check if everything were registered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_sad1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) goto enodev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) if (saw_chan_mask != 0x0f && /* -EN/-EX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) saw_chan_mask != 0x03) /* -EP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) goto enodev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) enodev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) static int knl_mci_bind_devs(struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) struct sbridge_dev *sbridge_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) struct sbridge_pvt *pvt = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) int dev, func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) int devidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) for (i = 0; i < sbridge_dev->n_devs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) pdev = sbridge_dev->pdev[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) if (!pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) /* Extract PCI device and function. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) dev = (pdev->devfn >> 3) & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) func = pdev->devfn & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) switch (pdev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) case PCI_DEVICE_ID_INTEL_KNL_IMC_MC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) if (dev == 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) pvt->knl.pci_mc0 = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) else if (dev == 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) pvt->knl.pci_mc1 = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) sbridge_printk(KERN_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) "Memory controller in unexpected place! (dev %d, fn %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) dev, func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) case PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) pvt->pci_sad0 = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) case PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) pvt->pci_sad1 = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) case PCI_DEVICE_ID_INTEL_KNL_IMC_CHA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) /* There are one of these per tile, and range from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) * 1.14.0 to 1.18.5.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) devidx = ((dev-14)*8)+func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) if (devidx < 0 || devidx >= KNL_MAX_CHAS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) sbridge_printk(KERN_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) "Caching and Home Agent in unexpected place! (dev %d, fn %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) dev, func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) WARN_ON(pvt->knl.pci_cha[devidx] != NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) pvt->knl.pci_cha[devidx] = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) case PCI_DEVICE_ID_INTEL_KNL_IMC_CHAN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) devidx = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) * MC0 channels 0-2 are device 9 function 2-4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) * MC1 channels 3-5 are device 8 function 2-4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) if (dev == 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) devidx = func-2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) else if (dev == 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) devidx = 3 + (func-2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) if (devidx < 0 || devidx >= KNL_MAX_CHANNELS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) sbridge_printk(KERN_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) "DRAM Channel Registers in unexpected place! (dev %d, fn %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) dev, func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) WARN_ON(pvt->knl.pci_channel[devidx] != NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) pvt->knl.pci_channel[devidx] = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) case PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) pvt->knl.pci_mc_info = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) case PCI_DEVICE_ID_INTEL_KNL_IMC_TA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) pvt->pci_ta = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) sbridge_printk(KERN_ERR, "Unexpected device %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) pdev->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) if (!pvt->knl.pci_mc0 || !pvt->knl.pci_mc1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) !pvt->pci_sad0 || !pvt->pci_sad1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) !pvt->pci_ta) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) goto enodev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) for (i = 0; i < KNL_MAX_CHANNELS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) if (!pvt->knl.pci_channel[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) sbridge_printk(KERN_ERR, "Missing channel %d\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) goto enodev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) for (i = 0; i < KNL_MAX_CHAS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) if (!pvt->knl.pci_cha[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) sbridge_printk(KERN_ERR, "Missing CHA %d\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) goto enodev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) enodev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) Error check routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) * While Sandy Bridge has error count registers, SMI BIOS read values from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) * and resets the counters. So, they are not reliable for the OS to read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) * from them. So, we have no option but to just trust on whatever MCE is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) * telling us about the errors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) static void sbridge_mce_output_error(struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) const struct mce *m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) struct mem_ctl_info *new_mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) struct sbridge_pvt *pvt = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) enum hw_event_mc_err_type tp_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) char *optype, msg[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) bool overflow = GET_BITFIELD(m->status, 62, 62);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) bool recoverable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) u32 mscod = GET_BITFIELD(m->status, 16, 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) u32 errcode = GET_BITFIELD(m->status, 0, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) u32 channel = GET_BITFIELD(m->status, 0, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) u32 optypenum = GET_BITFIELD(m->status, 4, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) * Bits 5-0 of MCi_MISC give the least significant bit that is valid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) * A value 6 is for cache line aligned address, a value 12 is for page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) * aligned address reported by patrol scrubber.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) u32 lsb = GET_BITFIELD(m->misc, 0, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) long channel_mask, first_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) u8 rank = 0xff, socket, ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) int rc, dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) char *area_type = "DRAM";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) if (pvt->info.type != SANDY_BRIDGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) recoverable = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) recoverable = GET_BITFIELD(m->status, 56, 56);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) if (uncorrected_error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) core_err_cnt = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) if (ripv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) tp_event = HW_EVENT_ERR_UNCORRECTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) tp_event = HW_EVENT_ERR_FATAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) tp_event = HW_EVENT_ERR_CORRECTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) * According with Table 15-9 of the Intel Architecture spec vol 3A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) * memory errors should fit in this mask:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) * 000f 0000 1mmm cccc (binary)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) * where:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) * f = Correction Report Filtering Bit. If 1, subsequent errors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) * won't be shown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) * mmm = error type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) * cccc = channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) * If the mask doesn't match, report an error to the parsing logic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) switch (optypenum) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) optype = "generic undef request error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) optype = "memory read error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) optype = "memory write error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) optype = "addr/cmd error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) optype = "memory scrubbing error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) optype = "reserved";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) if (pvt->info.type == KNIGHTS_LANDING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) if (channel == 14) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) edac_dbg(0, "%s%s err_code:%04x:%04x EDRAM bank %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) overflow ? " OVERFLOW" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) (uncorrected_error && recoverable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) ? " recoverable" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) mscod, errcode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) m->bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) char A = *("A");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) * Reported channel is in range 0-2, so we can't map it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) * back to mc. To figure out mc we check machine check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) * bank register that reported this error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) * bank15 means mc0 and bank16 means mc1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) channel = knl_channel_remap(m->bank == 16, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) channel_mask = 1 << channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) snprintf(msg, sizeof(msg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) "%s%s err_code:%04x:%04x channel:%d (DIMM_%c)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) overflow ? " OVERFLOW" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) (uncorrected_error && recoverable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) ? " recoverable" : " ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) mscod, errcode, channel, A + channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) edac_mc_handle_error(tp_event, mci, core_err_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) channel, 0, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) optype, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) } else if (lsb < 12) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) rc = get_memory_error_data(mci, m->addr, &socket, &ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) &channel_mask, &rank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) &area_type, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) rc = get_memory_error_data_from_mce(mci, m, &socket, &ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) &channel_mask, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) goto err_parsing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) new_mci = get_mci_for_node_id(socket, ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) if (!new_mci) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) strcpy(msg, "Error: socket got corrupted!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) goto err_parsing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) mci = new_mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) pvt = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) first_channel = find_first_bit(&channel_mask, NUM_CHANNELS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) if (rank == 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) dimm = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) else if (rank < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) dimm = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) else if (rank < 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) dimm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) dimm = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) * FIXME: On some memory configurations (mirror, lockstep), the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) * Memory Controller can't point the error to a single DIMM. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) * EDAC core should be handling the channel mask, in order to point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) * to the group of dimm's where the error may be happening.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) if (!pvt->is_lockstep && !pvt->is_cur_addr_mirrored && !pvt->is_close_pg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) channel = first_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) snprintf(msg, sizeof(msg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) "%s%s area:%s err_code:%04x:%04x socket:%d ha:%d channel_mask:%ld rank:%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) overflow ? " OVERFLOW" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) (uncorrected_error && recoverable) ? " recoverable" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) area_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) mscod, errcode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) socket, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) channel_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) rank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) edac_dbg(0, "%s\n", msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) /* FIXME: need support for channel mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) if (channel == CHANNEL_UNSPECIFIED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) channel = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) /* Call the helper to output message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) edac_mc_handle_error(tp_event, mci, core_err_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) channel, dimm, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) optype, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) err_parsing:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) edac_mc_handle_error(tp_event, mci, core_err_cnt, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) -1, -1, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) msg, "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) * Check that logging is enabled and that this is the right type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) * of error for us to handle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) struct mce *mce = (struct mce *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) struct mem_ctl_info *mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) char *type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) if (mce->kflags & MCE_HANDLED_CEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) * Just let mcelog handle it if the error is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) * outside the memory controller. A memory error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) * bit 12 has an special meaning.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) if ((mce->status & 0xefff) >> 7 != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) /* Check ADDRV bit in STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) if (!GET_BITFIELD(mce->status, 58, 58))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) /* Check MISCV bit in STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) if (!GET_BITFIELD(mce->status, 59, 59))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) /* Check address type in MISC (physical address only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) if (GET_BITFIELD(mce->misc, 6, 8) != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) mci = get_mci_for_node_id(mce->socketid, IMC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) if (!mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) if (mce->mcgstatus & MCG_STATUS_MCIP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) type = "Exception";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) type = "Event";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) sbridge_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) sbridge_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: %Lx "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) "Bank %d: %016Lx\n", mce->extcpu, type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) mce->mcgstatus, mce->bank, mce->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) sbridge_mc_printk(mci, KERN_DEBUG, "TSC %llx ", mce->tsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) sbridge_mc_printk(mci, KERN_DEBUG, "ADDR %llx ", mce->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) sbridge_mc_printk(mci, KERN_DEBUG, "MISC %llx ", mce->misc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) sbridge_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:%x TIME %llu SOCKET "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) "%u APIC %x\n", mce->cpuvendor, mce->cpuid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) mce->time, mce->socketid, mce->apicid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) sbridge_mce_output_error(mci, mce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) /* Advice mcelog that the error were handled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) mce->kflags |= MCE_HANDLED_EDAC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) static struct notifier_block sbridge_mce_dec = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) .notifier_call = sbridge_mce_check_error,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) .priority = MCE_PRIO_EDAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) EDAC register/unregister logic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) struct mem_ctl_info *mci = sbridge_dev->mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) if (unlikely(!mci || !mci->pvt_info)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) edac_dbg(0, "MC: dev = %p\n", &sbridge_dev->pdev[0]->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) sbridge_printk(KERN_ERR, "Couldn't find mci handler\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) edac_dbg(0, "MC: mci = %p, dev = %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) mci, &sbridge_dev->pdev[0]->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) /* Remove MC sysfs nodes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) edac_mc_del_mc(mci->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) edac_dbg(1, "%s: free mci struct\n", mci->ctl_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) kfree(mci->ctl_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) sbridge_dev->mci = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) struct mem_ctl_info *mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) struct edac_mc_layer layers[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) struct sbridge_pvt *pvt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) struct pci_dev *pdev = sbridge_dev->pdev[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) /* allocate a new MC control structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) layers[0].type = EDAC_MC_LAYER_CHANNEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) layers[0].size = type == KNIGHTS_LANDING ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) KNL_MAX_CHANNELS : NUM_CHANNELS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) layers[0].is_virt_csrow = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) layers[1].type = EDAC_MC_LAYER_SLOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) layers[1].size = type == KNIGHTS_LANDING ? 1 : MAX_DIMMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) layers[1].is_virt_csrow = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) mci = edac_mc_alloc(sbridge_dev->mc, ARRAY_SIZE(layers), layers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) sizeof(*pvt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) if (unlikely(!mci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) edac_dbg(0, "MC: mci = %p, dev = %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) mci, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) pvt = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) memset(pvt, 0, sizeof(*pvt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) /* Associate sbridge_dev and mci for future usage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) pvt->sbridge_dev = sbridge_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) sbridge_dev->mci = mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) mci->mtype_cap = type == KNIGHTS_LANDING ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) MEM_FLAG_DDR4 : MEM_FLAG_DDR3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) mci->edac_ctl_cap = EDAC_FLAG_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) mci->edac_cap = EDAC_FLAG_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) mci->mod_name = EDAC_MOD_STR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) mci->dev_name = pci_name(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) mci->ctl_page_to_phys = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) pvt->info.type = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) case IVY_BRIDGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) pvt->info.rankcfgr = IB_RANK_CFG_A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) pvt->info.get_tolm = ibridge_get_tolm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) pvt->info.get_tohm = ibridge_get_tohm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) pvt->info.dram_rule = ibridge_dram_rule;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) pvt->info.get_memory_type = get_memory_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) pvt->info.get_node_id = get_node_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) pvt->info.get_ha = ibridge_get_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) pvt->info.rir_limit = rir_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) pvt->info.sad_limit = sad_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) pvt->info.interleave_mode = interleave_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) pvt->info.dram_attr = dram_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) pvt->info.interleave_list = ibridge_interleave_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) pvt->info.interleave_pkg = ibridge_interleave_pkg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) pvt->info.get_width = ibridge_get_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) /* Store pci devices at mci for faster access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) rc = ibridge_mci_bind_devs(mci, sbridge_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) if (unlikely(rc < 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) goto fail0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) get_source_id(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) mci->ctl_name = kasprintf(GFP_KERNEL, "Ivy Bridge SrcID#%d_Ha#%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) case SANDY_BRIDGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) pvt->info.rankcfgr = SB_RANK_CFG_A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) pvt->info.get_tolm = sbridge_get_tolm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) pvt->info.get_tohm = sbridge_get_tohm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) pvt->info.dram_rule = sbridge_dram_rule;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) pvt->info.get_memory_type = get_memory_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) pvt->info.get_node_id = get_node_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) pvt->info.get_ha = sbridge_get_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) pvt->info.rir_limit = rir_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) pvt->info.sad_limit = sad_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) pvt->info.interleave_mode = interleave_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) pvt->info.dram_attr = dram_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) pvt->info.max_sad = ARRAY_SIZE(sbridge_dram_rule);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) pvt->info.interleave_list = sbridge_interleave_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) pvt->info.interleave_pkg = sbridge_interleave_pkg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) pvt->info.get_width = sbridge_get_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) /* Store pci devices at mci for faster access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) rc = sbridge_mci_bind_devs(mci, sbridge_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) if (unlikely(rc < 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) goto fail0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) get_source_id(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge SrcID#%d_Ha#%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) case HASWELL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) /* rankcfgr isn't used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) pvt->info.get_tolm = haswell_get_tolm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) pvt->info.get_tohm = haswell_get_tohm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) pvt->info.dram_rule = ibridge_dram_rule;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) pvt->info.get_memory_type = haswell_get_memory_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) pvt->info.get_node_id = haswell_get_node_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) pvt->info.get_ha = ibridge_get_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) pvt->info.rir_limit = haswell_rir_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) pvt->info.sad_limit = sad_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) pvt->info.interleave_mode = interleave_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) pvt->info.dram_attr = dram_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) pvt->info.interleave_list = ibridge_interleave_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) pvt->info.interleave_pkg = ibridge_interleave_pkg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) pvt->info.get_width = ibridge_get_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) /* Store pci devices at mci for faster access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) rc = haswell_mci_bind_devs(mci, sbridge_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) if (unlikely(rc < 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) goto fail0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) get_source_id(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) mci->ctl_name = kasprintf(GFP_KERNEL, "Haswell SrcID#%d_Ha#%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) case BROADWELL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) /* rankcfgr isn't used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) pvt->info.get_tolm = haswell_get_tolm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) pvt->info.get_tohm = haswell_get_tohm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) pvt->info.dram_rule = ibridge_dram_rule;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) pvt->info.get_memory_type = haswell_get_memory_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) pvt->info.get_node_id = haswell_get_node_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) pvt->info.get_ha = ibridge_get_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) pvt->info.rir_limit = haswell_rir_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) pvt->info.sad_limit = sad_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) pvt->info.interleave_mode = interleave_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) pvt->info.dram_attr = dram_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) pvt->info.interleave_list = ibridge_interleave_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) pvt->info.interleave_pkg = ibridge_interleave_pkg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) pvt->info.get_width = broadwell_get_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) /* Store pci devices at mci for faster access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) rc = broadwell_mci_bind_devs(mci, sbridge_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) if (unlikely(rc < 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) goto fail0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) get_source_id(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) mci->ctl_name = kasprintf(GFP_KERNEL, "Broadwell SrcID#%d_Ha#%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) case KNIGHTS_LANDING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) /* pvt->info.rankcfgr == ??? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) pvt->info.get_tolm = knl_get_tolm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) pvt->info.get_tohm = knl_get_tohm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) pvt->info.dram_rule = knl_dram_rule;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) pvt->info.get_memory_type = knl_get_memory_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) pvt->info.get_node_id = knl_get_node_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) pvt->info.get_ha = knl_get_ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) pvt->info.rir_limit = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) pvt->info.sad_limit = knl_sad_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) pvt->info.interleave_mode = knl_interleave_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) pvt->info.dram_attr = dram_attr_knl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) pvt->info.max_sad = ARRAY_SIZE(knl_dram_rule);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) pvt->info.interleave_list = knl_interleave_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) pvt->info.interleave_pkg = ibridge_interleave_pkg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) pvt->info.get_width = knl_get_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) rc = knl_mci_bind_devs(mci, sbridge_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) if (unlikely(rc < 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) goto fail0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) get_source_id(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) mci->ctl_name = kasprintf(GFP_KERNEL, "Knights Landing SrcID#%d_Ha#%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) if (!mci->ctl_name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) goto fail0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) /* Get dimm basic config and the memory layout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) rc = get_dimm_config(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) edac_dbg(0, "MC: failed to get_dimm_config()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) get_memory_layout(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) /* record ptr to the generic device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) mci->pdev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) /* add this new MC control structure to EDAC's list of MCs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) if (unlikely(edac_mc_add_mc(mci))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) kfree(mci->ctl_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) fail0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) sbridge_dev->mci = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) static const struct x86_cpu_id sbridge_cpuids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE_X, &pci_dev_descr_sbridge_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X, &pci_dev_descr_ibridge_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, &pci_dev_descr_haswell_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, &pci_dev_descr_broadwell_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D, &pci_dev_descr_broadwell_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &pci_dev_descr_knl_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &pci_dev_descr_knl_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) MODULE_DEVICE_TABLE(x86cpu, sbridge_cpuids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) * sbridge_probe Get all devices and register memory controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) * present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) * return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) * 0 for FOUND a device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) * < 0 for error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) static int sbridge_probe(const struct x86_cpu_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) int rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) u8 mc, num_mc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) struct sbridge_dev *sbridge_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) struct pci_id_table *ptable = (struct pci_id_table *)id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) /* get the pci devices we want to reserve for our use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) rc = sbridge_get_all_devices(&num_mc, ptable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) if (unlikely(rc < 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) edac_dbg(0, "couldn't get all devices\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) goto fail0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) mc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) edac_dbg(0, "Registering MC#%d (%d of %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) mc, mc + 1, num_mc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) sbridge_dev->mc = mc++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) rc = sbridge_register_mci(sbridge_dev, ptable->type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) if (unlikely(rc < 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) goto fail1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) sbridge_printk(KERN_INFO, "%s\n", SBRIDGE_REVISION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) fail1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) sbridge_unregister_mci(sbridge_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) sbridge_put_all_devices();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) fail0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) * sbridge_remove cleanup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) static void sbridge_remove(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) struct sbridge_dev *sbridge_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) edac_dbg(0, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) sbridge_unregister_mci(sbridge_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) /* Release PCI resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) sbridge_put_all_devices();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) * sbridge_init Module entry function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) * Try to initialize this module for its devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) static int __init sbridge_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) const struct x86_cpu_id *id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) const char *owner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) edac_dbg(2, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) owner = edac_get_owner();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) if (cpu_feature_enabled(X86_FEATURE_HYPERVISOR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) id = x86_match_cpu(sbridge_cpuids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) if (!id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) /* Ensure that the OPSTATE is set correctly for POLL or NMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) opstate_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) rc = sbridge_probe(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) if (rc >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) mce_register_decode_chain(&sbridge_mce_dec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) sbridge_printk(KERN_ERR, "Failed to register device with error %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) * sbridge_exit() Module exit function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) * Unregister the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) static void __exit sbridge_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) edac_dbg(2, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) sbridge_remove();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) mce_unregister_decode_chain(&sbridge_mce_dec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) module_init(sbridge_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) module_exit(sbridge_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) module_param(edac_op_state, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) MODULE_AUTHOR("Mauro Carvalho Chehab");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) MODULE_AUTHOR("Red Hat Inc. (https://www.redhat.com)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge and Ivy Bridge memory controllers - "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) SBRIDGE_REVISION);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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