^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Radisys 82600 Embedded chipset Memory Controller kernel module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * (C) 2005 EADS Astrium
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This file may be distributed under the terms of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * GNU General Public License.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Written by Tim Small <tim@buttersideup.com>, based on work by Thayne
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Harbaugh, Dan Hollis <goemon at anime dot net> and others.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * $Id: edac_r82600.c,v 1.1.2.6 2005/10/05 00:43:44 dsp_llnl Exp $
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Written with reference to 82600 High Integration Dual PCI System
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Controller Data Book:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * www.radisys.com/files/support_downloads/007-01277-0002.82600DataBook.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * references to this document given in []
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pci_ids.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/edac.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "edac_module.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define EDAC_MOD_STR "r82600_edac"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define r82600_printk(level, fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) edac_printk(level, "r82600", fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define r82600_mc_printk(mci, level, fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) edac_mc_chipset_printk(mci, level, "r82600", fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Radisys say "The 82600 integrates a main memory SDRAM controller that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * supports up to four banks of memory. The four banks can support a mix of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * sizes of 64 bit wide (72 bits with ECC) Synchronous DRAM (SDRAM) DIMMs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * each of which can be any size from 16MB to 512MB. Both registered (control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * signals buffered) and unbuffered DIMM types are supported. Mixing of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * registered and unbuffered DIMMs as well as mixing of ECC and non-ECC DIMMs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * is not allowed. The 82600 SDRAM interface operates at the same frequency as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * the CPU bus, 66MHz, 100MHz or 133MHz."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define R82600_NR_CSROWS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define R82600_NR_CHANS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define R82600_NR_DIMMS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define R82600_BRIDGE_ID 0x8200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Radisys 82600 register addresses - device 0 function 0 - PCI bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define R82600_DRAMC 0x57 /* Various SDRAM related control bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * all bits are R/W
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * 7 SDRAM ISA Hole Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * 6 Flash Page Mode Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * 5 ECC Enable: 1=ECC 0=noECC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * 4 DRAM DIMM Type: 1=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * 3 BIOS Alias Disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * 2 SDRAM BIOS Flash Write Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * 1:0 SDRAM Refresh Rate: 00=Disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * 01=7.8usec (256Mbit SDRAMs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * 10=15.6us 11=125usec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define R82600_SDRAMC 0x76 /* "SDRAM Control Register"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * More SDRAM related control bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * all bits are R/W
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * 15:8 Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * 7:5 Special SDRAM Mode Select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * 4 Force ECC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * 1=Drive ECC bits to 0 during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * write cycles (i.e. ECC test mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * 0=Normal ECC functioning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * 3 Enhanced Paging Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * 2 CAS# Latency 0=3clks 1=2clks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * 1 RAS# to CAS# Delay 0=3 1=2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * 0 RAS# Precharge 0=3 1=2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define R82600_EAP 0x80 /* ECC Error Address Pointer Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * 31 Disable Hardware Scrubbing (RW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * 0=Scrub on corrected read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * 1=Don't scrub on corrected read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * 30:12 Error Address Pointer (RO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * Upper 19 bits of error address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * 11:4 Syndrome Bits (RO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * 3 BSERR# on multibit error (RW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * 1=enable 0=disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * 2 NMI on Single Bit Eror (RW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * 1=NMI triggered by SBE n.b. other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * prerequeists
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * 0=NMI not triggered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * 1 MBE (R/WC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * read 1=MBE at EAP (see above)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * read 0=no MBE, or SBE occurred first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * write 1=Clear MBE status (must also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * clear SBE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * write 0=NOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * 1 SBE (R/WC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * read 1=SBE at EAP (see above)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * read 0=no SBE, or MBE occurred first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * write 1=Clear SBE status (must also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * clear MBE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * write 0=NOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define R82600_DRBA 0x60 /* + 0x60..0x63 SDRAM Row Boundary Address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * 7:0 Address lines 30:24 - upper limit of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * each row [p57]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct r82600_error_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 eapr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static bool disable_hardware_scrub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static struct edac_pci_ctl_info *r82600_pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static void r82600_get_error_info(struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct r82600_error_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) pdev = to_pci_dev(mci->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) pci_read_config_dword(pdev, R82600_EAP, &info->eapr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (info->eapr & BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Clear error to allow next error to be reported [p.62] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) pci_write_bits32(pdev, R82600_EAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ((u32) BIT(0) & (u32) BIT(1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ((u32) BIT(0) & (u32) BIT(1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (info->eapr & BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Clear error to allow next error to be reported [p.62] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) pci_write_bits32(pdev, R82600_EAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ((u32) BIT(0) & (u32) BIT(1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ((u32) BIT(0) & (u32) BIT(1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int r82600_process_error_info(struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct r82600_error_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int handle_errors)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int error_found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u32 eapaddr, page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u32 syndrome;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) error_found = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* bits 30:12 store the upper 19 bits of the 32 bit error address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) eapaddr = ((info->eapr >> 12) & 0x7FFF) << 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* Syndrome in bits 11:4 [p.62] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) syndrome = (info->eapr >> 4) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* the R82600 reports at less than page *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * granularity (upper 19 bits only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) page = eapaddr >> PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (info->eapr & BIT(0)) { /* CE? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) error_found = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (handle_errors)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) page, 0, syndrome,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) edac_mc_find_csrow_by_page(mci, page),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 0, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) mci->ctl_name, "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (info->eapr & BIT(1)) { /* UE? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) error_found = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (handle_errors)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* 82600 doesn't give enough info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) page, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) edac_mc_find_csrow_by_page(mci, page),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 0, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) mci->ctl_name, "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return error_found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static void r82600_check(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct r82600_error_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) edac_dbg(1, "MC%d\n", mci->mc_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) r82600_get_error_info(mci, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) r82600_process_error_info(mci, &info, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static inline int ecc_enabled(u8 dramcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return dramcr & BIT(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static void r82600_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u8 dramcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct csrow_info *csrow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct dimm_info *dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u8 drbar; /* SDRAM Row Boundary Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u32 row_high_limit, row_high_limit_last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u32 reg_sdram, ecc_on, row_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ecc_on = ecc_enabled(dramcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) reg_sdram = dramcr & BIT(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) row_high_limit_last = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) for (index = 0; index < mci->nr_csrows; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) csrow = mci->csrows[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) dimm = csrow->channels[0]->dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* find the DRAM Chip Select Base address and mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) pci_read_config_byte(pdev, R82600_DRBA + index, &drbar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) edac_dbg(1, "Row=%d DRBA = %#0x\n", index, drbar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) row_high_limit = ((u32) drbar << 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* row_high_limit = ((u32)drbar << 24) | 0xffffffUL; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) edac_dbg(1, "Row=%d, Boundary Address=%#0x, Last = %#0x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) index, row_high_limit, row_high_limit_last);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* Empty row [p.57] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (row_high_limit == row_high_limit_last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) row_base = row_high_limit_last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) csrow->first_page = row_base >> PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) dimm->nr_pages = csrow->last_page - csrow->first_page + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* Error address is top 19 bits - so granularity is *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * 14 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) dimm->grain = 1 << 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) dimm->mtype = reg_sdram ? MEM_RDDR : MEM_DDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* FIXME - check that this is unknowable with this chipset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) dimm->dtype = DEV_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* Mode is global on 82600 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) dimm->edac_mode = ecc_on ? EDAC_SECDED : EDAC_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) row_high_limit_last = row_high_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int r82600_probe1(struct pci_dev *pdev, int dev_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct mem_ctl_info *mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct edac_mc_layer layers[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u8 dramcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u32 eapr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u32 scrub_disabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) u32 sdram_refresh_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct r82600_error_info discard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) edac_dbg(0, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) pci_read_config_byte(pdev, R82600_DRAMC, &dramcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) pci_read_config_dword(pdev, R82600_EAP, &eapr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) scrub_disabled = eapr & BIT(31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) sdram_refresh_rate = dramcr & (BIT(0) | BIT(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) edac_dbg(2, "sdram refresh rate = %#0x\n", sdram_refresh_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) edac_dbg(2, "DRAMC register = %#0x\n", dramcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) layers[0].size = R82600_NR_CSROWS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) layers[0].is_virt_csrow = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) layers[1].type = EDAC_MC_LAYER_CHANNEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) layers[1].size = R82600_NR_CHANS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) layers[1].is_virt_csrow = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (mci == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) edac_dbg(0, "mci = %p\n", mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) mci->pdev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_DDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* FIXME try to work out if the chip leads have been used for COM2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * instead on this board? [MA6?] MAYBE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* On the R82600, the pins for memory bits 72:65 - i.e. the *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * EC bits are shared with the pins for COM2 (!), so if COM2 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * is enabled, we assume COM2 is wired up, and thus no EDAC *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * is possible. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) mci->edac_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (ecc_enabled(dramcr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (scrub_disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) edac_dbg(3, "mci = %p - Scrubbing disabled! EAP: %#0x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) mci, eapr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) mci->edac_cap = EDAC_FLAG_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) mci->mod_name = EDAC_MOD_STR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) mci->ctl_name = "R82600";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) mci->dev_name = pci_name(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) mci->edac_check = r82600_check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) mci->ctl_page_to_phys = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) r82600_init_csrows(mci, pdev, dramcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) r82600_get_error_info(mci, &discard); /* clear counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* Here we assume that we will never see multiple instances of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * type of memory controller. The ID is therefore hardcoded to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (edac_mc_add_mc(mci)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) edac_dbg(3, "failed edac_mc_add_mc()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* get this far and it's successful */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (disable_hardware_scrub) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) edac_dbg(3, "Disabling Hardware Scrub (scrub on error)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) pci_write_bits32(pdev, R82600_EAP, BIT(31), BIT(31));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* allocating generic PCI control info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) r82600_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (!r82600_pci) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) "%s(): Unable to create PCI control\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) "%s(): PCI error report via EDAC not setup\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) edac_dbg(3, "success\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* returns count (>= 0), or negative on error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static int r82600_init_one(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) edac_dbg(0, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* don't need to call pci_enable_device() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return r82600_probe1(pdev, ent->driver_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static void r82600_remove_one(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct mem_ctl_info *mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) edac_dbg(0, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (r82600_pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) edac_pci_release_generic_ctl(r82600_pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static const struct pci_device_id r82600_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) PCI_DEVICE(PCI_VENDOR_ID_RADISYS, R82600_BRIDGE_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) } /* 0 terminated list. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) MODULE_DEVICE_TABLE(pci, r82600_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static struct pci_driver r82600_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .name = EDAC_MOD_STR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .probe = r82600_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .remove = r82600_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .id_table = r82600_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static int __init r82600_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* Ensure that the OPSTATE is set correctly for POLL or NMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) opstate_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return pci_register_driver(&r82600_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static void __exit r82600_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) pci_unregister_driver(&r82600_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) module_init(r82600_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) module_exit(r82600_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD Ltd. "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) "on behalf of EADS Astrium");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) MODULE_DESCRIPTION("MC support for Radisys 82600 memory controllers");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) module_param(disable_hardware_scrub, bool, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) MODULE_PARM_DESC(disable_hardware_scrub,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) "If set, disable the chipset's automatic scrub for CEs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) module_param(edac_op_state, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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