^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/edac.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/soc/qcom/llcc-qcom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "edac_mc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "edac_device.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define EDAC_LLCC "qcom_llcc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define LLCC_ERP_PANIC_ON_UE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TRP_SYN_REG_CNT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DRP_SYN_REG_CNT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define LLCC_COMMON_STATUS0 0x0003000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define LLCC_LB_CNT_MASK GENMASK(31, 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define LLCC_LB_CNT_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Single & double bit syndrome register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TRP_ECC_SB_ERR_SYN0 0x0002304c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TRP_ECC_DB_ERR_SYN0 0x00020370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DRP_ECC_SB_ERR_SYN0 0x0004204c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DRP_ECC_DB_ERR_SYN0 0x00042070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Error register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TRP_ECC_ERROR_STATUS1 0x00020348
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TRP_ECC_ERROR_STATUS0 0x00020344
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DRP_ECC_ERROR_STATUS1 0x00042048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DRP_ECC_ERROR_STATUS0 0x00042044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* TRP, DRP interrupt register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DRP_INTERRUPT_STATUS 0x00041000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TRP_INTERRUPT_0_STATUS 0x00020480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DRP_INTERRUPT_CLEAR 0x00041008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DRP_ECC_ERROR_CNTR_CLEAR 0x00040004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TRP_INTERRUPT_0_CLEAR 0x00020484
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TRP_ECC_ERROR_CNTR_CLEAR 0x00020440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Mask and shift macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ECC_DB_ERR_COUNT_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ECC_DB_ERR_WAYS_MASK GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ECC_DB_ERR_WAYS_SHIFT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ECC_SB_ERR_COUNT_MASK GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ECC_SB_ERR_COUNT_SHIFT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ECC_SB_ERR_WAYS_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SB_ECC_ERROR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DB_ECC_ERROR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DRP_TRP_INT_CLEAR GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DRP_TRP_CNT_CLEAR GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* Config registers offsets*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DRP_ECC_ERROR_CFG 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* Tag RAM, Data RAM interrupt register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CMN_INTERRUPT_0_ENABLE 0x0003001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CMN_INTERRUPT_2_ENABLE 0x0003003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define TRP_INTERRUPT_0_ENABLE 0x00020488
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DRP_INTERRUPT_ENABLE 0x0004100c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SB_ERROR_THRESHOLD 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SB_ERROR_THRESHOLD_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SB_DB_TRP_INTERRUPT_ENABLE 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define TRP0_INTERRUPT_ENABLE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define DRP0_INTERRUPT_ENABLE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SB_DB_DRP_INTERRUPT_ENABLE 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) LLCC_DRAM_CE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) LLCC_DRAM_UE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) LLCC_TRAM_CE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) LLCC_TRAM_UE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static const struct llcc_edac_reg_data edac_reg_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) [LLCC_DRAM_CE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .name = "DRAM Single-bit",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .synd_reg = DRP_ECC_SB_ERR_SYN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .count_status_reg = DRP_ECC_ERROR_STATUS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .ways_status_reg = DRP_ECC_ERROR_STATUS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .reg_cnt = DRP_SYN_REG_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .count_mask = ECC_SB_ERR_COUNT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .ways_mask = ECC_SB_ERR_WAYS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .count_shift = ECC_SB_ERR_COUNT_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) [LLCC_DRAM_UE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .name = "DRAM Double-bit",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .synd_reg = DRP_ECC_DB_ERR_SYN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .count_status_reg = DRP_ECC_ERROR_STATUS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .ways_status_reg = DRP_ECC_ERROR_STATUS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .reg_cnt = DRP_SYN_REG_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .count_mask = ECC_DB_ERR_COUNT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .ways_mask = ECC_DB_ERR_WAYS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .ways_shift = ECC_DB_ERR_WAYS_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) [LLCC_TRAM_CE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .name = "TRAM Single-bit",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .synd_reg = TRP_ECC_SB_ERR_SYN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .count_status_reg = TRP_ECC_ERROR_STATUS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .ways_status_reg = TRP_ECC_ERROR_STATUS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .reg_cnt = TRP_SYN_REG_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .count_mask = ECC_SB_ERR_COUNT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .ways_mask = ECC_SB_ERR_WAYS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .count_shift = ECC_SB_ERR_COUNT_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) [LLCC_TRAM_UE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .name = "TRAM Double-bit",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .synd_reg = TRP_ECC_DB_ERR_SYN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .count_status_reg = TRP_ECC_ERROR_STATUS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .ways_status_reg = TRP_ECC_ERROR_STATUS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .reg_cnt = TRP_SYN_REG_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .count_mask = ECC_DB_ERR_COUNT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .ways_mask = ECC_DB_ERR_WAYS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .ways_shift = ECC_DB_ERR_WAYS_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static int qcom_llcc_core_setup(struct regmap *llcc_bcast_regmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 sb_err_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * Configure interrupt enable registers such that Tag, Data RAM related
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * interrupts are propagated to interrupt controller for servicing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ret = regmap_update_bits(llcc_bcast_regmap, CMN_INTERRUPT_2_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) TRP0_INTERRUPT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) TRP0_INTERRUPT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) ret = regmap_update_bits(llcc_bcast_regmap, TRP_INTERRUPT_0_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) SB_DB_TRP_INTERRUPT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) SB_DB_TRP_INTERRUPT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) sb_err_threshold = (SB_ERROR_THRESHOLD << SB_ERROR_THRESHOLD_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ret = regmap_write(llcc_bcast_regmap, DRP_ECC_ERROR_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) sb_err_threshold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ret = regmap_update_bits(llcc_bcast_regmap, CMN_INTERRUPT_2_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) DRP0_INTERRUPT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) DRP0_INTERRUPT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ret = regmap_write(llcc_bcast_regmap, DRP_INTERRUPT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) SB_DB_DRP_INTERRUPT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Clear the error interrupt and counter registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) qcom_llcc_clear_error_status(int err_type, struct llcc_drv_data *drv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) switch (err_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) case LLCC_DRAM_CE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) case LLCC_DRAM_UE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ret = regmap_write(drv->bcast_regmap, DRP_INTERRUPT_CLEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) DRP_TRP_INT_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ret = regmap_write(drv->bcast_regmap, DRP_ECC_ERROR_CNTR_CLEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) DRP_TRP_CNT_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) case LLCC_TRAM_CE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) case LLCC_TRAM_UE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ret = regmap_write(drv->bcast_regmap, TRP_INTERRUPT_0_CLEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) DRP_TRP_INT_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ret = regmap_write(drv->bcast_regmap, TRP_ECC_ERROR_CNTR_CLEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) DRP_TRP_CNT_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) edac_printk(KERN_CRIT, EDAC_LLCC, "Unexpected error type: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) err_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Dump Syndrome registers data for Tag RAM, Data RAM bit errors*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int err_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct llcc_edac_reg_data reg_data = edac_reg_data[err_type];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int err_cnt, err_ways, ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u32 synd_reg, synd_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) for (i = 0; i < reg_data.reg_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) synd_reg = reg_data.synd_reg + (i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) &synd_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) goto clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) edac_printk(KERN_CRIT, EDAC_LLCC, "%s: ECC_SYN%d: 0x%8x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) reg_data.name, i, synd_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ret = regmap_read(drv->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) drv->offsets[bank] + reg_data.count_status_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) &err_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) goto clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) err_cnt &= reg_data.count_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) err_cnt >>= reg_data.count_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) edac_printk(KERN_CRIT, EDAC_LLCC, "%s: Error count: 0x%4x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) reg_data.name, err_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ret = regmap_read(drv->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) drv->offsets[bank] + reg_data.ways_status_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) &err_ways);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) goto clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) err_ways &= reg_data.ways_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) err_ways >>= reg_data.ways_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) edac_printk(KERN_CRIT, EDAC_LLCC, "%s: Error ways: 0x%4x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) reg_data.name, err_ways);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) clear:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return qcom_llcc_clear_error_status(err_type, drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) dump_syn_reg(struct edac_device_ctl_info *edev_ctl, int err_type, u32 bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct llcc_drv_data *drv = edev_ctl->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ret = dump_syn_reg_values(drv, bank, err_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) switch (err_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) case LLCC_DRAM_CE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) edac_device_handle_ce(edev_ctl, 0, bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) "LLCC Data RAM correctable Error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) case LLCC_DRAM_UE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) edac_device_handle_ue(edev_ctl, 0, bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) "LLCC Data RAM uncorrectable Error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) case LLCC_TRAM_CE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) edac_device_handle_ce(edev_ctl, 0, bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) "LLCC Tag RAM correctable Error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) case LLCC_TRAM_UE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) edac_device_handle_ue(edev_ctl, 0, bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) "LLCC Tag RAM uncorrectable Error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) edac_printk(KERN_CRIT, EDAC_LLCC, "Unexpected error type: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) err_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) llcc_ecc_irq_handler(int irq, void *edev_ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct edac_device_ctl_info *edac_dev_ctl = edev_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct llcc_drv_data *drv = edac_dev_ctl->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) irqreturn_t irq_rc = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u32 drp_error, trp_error, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* Iterate over the banks and look for Tag RAM or Data RAM errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) for (i = 0; i < drv->num_banks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ret = regmap_read(drv->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) drv->offsets[i] + DRP_INTERRUPT_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) &drp_error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (!ret && (drp_error & SB_ECC_ERROR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) edac_printk(KERN_CRIT, EDAC_LLCC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) "Single Bit Error detected in Data RAM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ret = dump_syn_reg(edev_ctl, LLCC_DRAM_CE, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) } else if (!ret && (drp_error & DB_ECC_ERROR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) edac_printk(KERN_CRIT, EDAC_LLCC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) "Double Bit Error detected in Data RAM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) ret = dump_syn_reg(edev_ctl, LLCC_DRAM_UE, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) irq_rc = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ret = regmap_read(drv->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) drv->offsets[i] + TRP_INTERRUPT_0_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) &trp_error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (!ret && (trp_error & SB_ECC_ERROR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) edac_printk(KERN_CRIT, EDAC_LLCC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) "Single Bit Error detected in Tag RAM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ret = dump_syn_reg(edev_ctl, LLCC_TRAM_CE, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) } else if (!ret && (trp_error & DB_ECC_ERROR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) edac_printk(KERN_CRIT, EDAC_LLCC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) "Double Bit Error detected in Tag RAM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ret = dump_syn_reg(edev_ctl, LLCC_TRAM_UE, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) irq_rc = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return irq_rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static int qcom_llcc_edac_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct llcc_drv_data *llcc_driv_data = pdev->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct edac_device_ctl_info *edev_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) int ecc_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) rc = qcom_llcc_core_setup(llcc_driv_data->bcast_regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* Allocate edac control info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) edev_ctl = edac_device_alloc_ctl_info(0, "qcom-llcc", 1, "bank",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) llcc_driv_data->num_banks, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) edac_device_alloc_index());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (!edev_ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) edev_ctl->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) edev_ctl->mod_name = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) edev_ctl->dev_name = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) edev_ctl->ctl_name = "llcc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) edev_ctl->panic_on_ue = LLCC_ERP_PANIC_ON_UE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) edev_ctl->pvt_info = llcc_driv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) rc = edac_device_add_device(edev_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) goto out_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) platform_set_drvdata(pdev, edev_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* Request for ecc irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) ecc_irq = llcc_driv_data->ecc_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (ecc_irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) goto out_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) rc = devm_request_irq(dev, ecc_irq, llcc_ecc_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) IRQF_TRIGGER_HIGH, "llcc_ecc", edev_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) goto out_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) out_dev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) edac_device_del_device(edev_ctl->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) out_mem:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) edac_device_free_ctl_info(edev_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static int qcom_llcc_edac_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct edac_device_ctl_info *edev_ctl = dev_get_drvdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) edac_device_del_device(edev_ctl->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) edac_device_free_ctl_info(edev_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static struct platform_driver qcom_llcc_edac_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .probe = qcom_llcc_edac_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .remove = qcom_llcc_edac_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .name = "qcom_llcc_edac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) module_platform_driver(qcom_llcc_edac_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) MODULE_DESCRIPTION("QCOM EDAC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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