Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2008 Nuovation System Designs, LLC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *   Grant Erickson <gerickson@nuovations.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * This file defines processor mnemonics for accessing and managing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * the IBM DDR1/DDR2 ECC controller found in the 405EX[r], 440SP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * 440SPe, 460EX, 460GT and 460SX.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #ifndef __PPC4XX_EDAC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define __PPC4XX_EDAC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * Macro for generating register field mnemonics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define PPC_REG_BITS			32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define PPC_REG_VAL(bit, val)		((val) << ((PPC_REG_BITS - 1) - (bit)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define PPC_REG_DECODE(bit, val)	((val) >> ((PPC_REG_BITS - 1) - (bit)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * IBM 4xx DDR1/DDR2 SDRAM memory controller registers (at least those
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * relevant to ECC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define SDRAM_BESR			0x00	/* Error status (read/clear) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define SDRAM_BESRT			0x01	/* Error statuss (test/set)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define SDRAM_BEARL			0x02	/* Error address low	     */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define SDRAM_BEARH			0x03	/* Error address high	     */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define SDRAM_WMIRQ			0x06	/* Write master (read/clear) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define SDRAM_WMIRQT			0x07	/* Write master (test/set)   */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define SDRAM_MCOPT1			0x20	/* Controller options 1	     */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define SDRAM_MBXCF_BASE		0x40	/* Bank n configuration base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define	SDRAM_MBXCF(n)			(SDRAM_MBXCF_BASE + (4 * (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define SDRAM_MB0CF			SDRAM_MBXCF(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define SDRAM_MB1CF			SDRAM_MBXCF(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define SDRAM_MB2CF			SDRAM_MBXCF(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define SDRAM_MB3CF			SDRAM_MBXCF(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define SDRAM_ECCCR			0x98	/* ECC error status	     */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define SDRAM_ECCES			SDRAM_ECCCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  * PLB Master IDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define	SDRAM_PLB_M0ID_FIRST		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define	SDRAM_PLB_M0ID_ICU		SDRAM_PLB_M0ID_FIRST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define	SDRAM_PLB_M0ID_PCIE0		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define	SDRAM_PLB_M0ID_PCIE1		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define	SDRAM_PLB_M0ID_DMA		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define	SDRAM_PLB_M0ID_DCU		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define	SDRAM_PLB_M0ID_OPB		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define	SDRAM_PLB_M0ID_MAL		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define	SDRAM_PLB_M0ID_SEC		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define	SDRAM_PLB_M0ID_AHB		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define SDRAM_PLB_M0ID_LAST		SDRAM_PLB_M0ID_AHB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define SDRAM_PLB_M0ID_COUNT		(SDRAM_PLB_M0ID_LAST - \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 					 SDRAM_PLB_M0ID_FIRST + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  * Memory Controller Bus Error Status Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define SDRAM_BESR_MASK			PPC_REG_VAL(7, 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define SDRAM_BESR_M0ID_MASK		PPC_REG_VAL(3, 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define	SDRAM_BESR_M0ID_DECODE(n)	PPC_REG_DECODE(3, n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define SDRAM_BESR_M0ID_ICU		PPC_REG_VAL(3, SDRAM_PLB_M0ID_ICU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define SDRAM_BESR_M0ID_PCIE0		PPC_REG_VAL(3, SDRAM_PLB_M0ID_PCIE0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define SDRAM_BESR_M0ID_PCIE1		PPC_REG_VAL(3, SDRAM_PLB_M0ID_PCIE1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define SDRAM_BESR_M0ID_DMA		PPC_REG_VAL(3, SDRAM_PLB_M0ID_DMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define SDRAM_BESR_M0ID_DCU		PPC_REG_VAL(3, SDRAM_PLB_M0ID_DCU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define SDRAM_BESR_M0ID_OPB		PPC_REG_VAL(3, SDRAM_PLB_M0ID_OPB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define SDRAM_BESR_M0ID_MAL		PPC_REG_VAL(3, SDRAM_PLB_M0ID_MAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define SDRAM_BESR_M0ID_SEC		PPC_REG_VAL(3, SDRAM_PLB_M0ID_SEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define SDRAM_BESR_M0ID_AHB		PPC_REG_VAL(3, SDRAM_PLB_M0ID_AHB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define SDRAM_BESR_M0ET_MASK		PPC_REG_VAL(6, 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define SDRAM_BESR_M0ET_NONE		PPC_REG_VAL(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define SDRAM_BESR_M0ET_ECC		PPC_REG_VAL(6, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define SDRAM_BESR_M0RW_MASK		PPC_REG_VAL(7, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define SDRAM_BESR_M0RW_WRITE		PPC_REG_VAL(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define SDRAM_BESR_M0RW_READ		PPC_REG_VAL(7, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)  * Memory Controller PLB Write Master Interrupt Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define SDRAM_WMIRQ_MASK		PPC_REG_VAL(8, 0x1FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define	SDRAM_WMIRQ_ENCODE(id)		PPC_REG_VAL((id % \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 						     SDRAM_PLB_M0ID_COUNT), 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define SDRAM_WMIRQ_ICU			PPC_REG_VAL(SDRAM_PLB_M0ID_ICU, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define SDRAM_WMIRQ_PCIE0		PPC_REG_VAL(SDRAM_PLB_M0ID_PCIE0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define SDRAM_WMIRQ_PCIE1		PPC_REG_VAL(SDRAM_PLB_M0ID_PCIE1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define SDRAM_WMIRQ_DMA			PPC_REG_VAL(SDRAM_PLB_M0ID_DMA, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define SDRAM_WMIRQ_DCU			PPC_REG_VAL(SDRAM_PLB_M0ID_DCU, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define SDRAM_WMIRQ_OPB			PPC_REG_VAL(SDRAM_PLB_M0ID_OPB, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define SDRAM_WMIRQ_MAL			PPC_REG_VAL(SDRAM_PLB_M0ID_MAL, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define SDRAM_WMIRQ_SEC			PPC_REG_VAL(SDRAM_PLB_M0ID_SEC, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define SDRAM_WMIRQ_AHB			PPC_REG_VAL(SDRAM_PLB_M0ID_AHB, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)  * Memory Controller Options 1 Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SDRAM_MCOPT1_MCHK_MASK	    PPC_REG_VAL(3, 0x3)	 /* ECC mask	     */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SDRAM_MCOPT1_MCHK_NON	    PPC_REG_VAL(3, 0x0)	 /* No ECC gen	     */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SDRAM_MCOPT1_MCHK_GEN	    PPC_REG_VAL(3, 0x2)	 /* ECC gen	     */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SDRAM_MCOPT1_MCHK_CHK	    PPC_REG_VAL(3, 0x1)	 /* ECC gen and chk  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SDRAM_MCOPT1_MCHK_CHK_REP   PPC_REG_VAL(3, 0x3)	 /* ECC gen/chk/rpt  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SDRAM_MCOPT1_MCHK_DECODE(n) ((((u32)(n)) >> 28) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SDRAM_MCOPT1_RDEN_MASK	    PPC_REG_VAL(4, 0x1)	 /* Rgstrd DIMM mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SDRAM_MCOPT1_RDEN	    PPC_REG_VAL(4, 0x1)	 /* Rgstrd DIMM enbl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SDRAM_MCOPT1_WDTH_MASK	    PPC_REG_VAL(7, 0x1)	 /* Width mask	     */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SDRAM_MCOPT1_WDTH_32	    PPC_REG_VAL(7, 0x0)	 /* 32 bits	     */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SDRAM_MCOPT1_WDTH_16	    PPC_REG_VAL(7, 0x1)	 /* 16 bits	     */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SDRAM_MCOPT1_DDR_TYPE_MASK  PPC_REG_VAL(11, 0x1) /* DDR type mask    */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SDRAM_MCOPT1_DDR1_TYPE	    PPC_REG_VAL(11, 0x0) /* DDR1 type	     */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SDRAM_MCOPT1_DDR2_TYPE	    PPC_REG_VAL(11, 0x1) /* DDR2 type	     */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)  * Memory Bank 0 - n Configuration Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SDRAM_MBCF_BA_MASK		PPC_REG_VAL(12, 0x1FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SDRAM_MBCF_SZ_MASK		PPC_REG_VAL(19, 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SDRAM_MBCF_SZ_DECODE(mbxcf)	PPC_REG_DECODE(19, mbxcf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SDRAM_MBCF_SZ_4MB		PPC_REG_VAL(19, 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SDRAM_MBCF_SZ_8MB		PPC_REG_VAL(19, 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SDRAM_MBCF_SZ_16MB		PPC_REG_VAL(19, 0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SDRAM_MBCF_SZ_32MB		PPC_REG_VAL(19, 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SDRAM_MBCF_SZ_64MB		PPC_REG_VAL(19, 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SDRAM_MBCF_SZ_128MB		PPC_REG_VAL(19, 0x5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SDRAM_MBCF_SZ_256MB		PPC_REG_VAL(19, 0x6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SDRAM_MBCF_SZ_512MB		PPC_REG_VAL(19, 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SDRAM_MBCF_SZ_1GB		PPC_REG_VAL(19, 0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SDRAM_MBCF_SZ_2GB		PPC_REG_VAL(19, 0x9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SDRAM_MBCF_SZ_4GB		PPC_REG_VAL(19, 0xA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SDRAM_MBCF_SZ_8GB		PPC_REG_VAL(19, 0xB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SDRAM_MBCF_AM_MASK		PPC_REG_VAL(23, 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SDRAM_MBCF_AM_MODE0		PPC_REG_VAL(23, 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SDRAM_MBCF_AM_MODE1		PPC_REG_VAL(23, 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SDRAM_MBCF_AM_MODE2		PPC_REG_VAL(23, 0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SDRAM_MBCF_AM_MODE3		PPC_REG_VAL(23, 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SDRAM_MBCF_AM_MODE4		PPC_REG_VAL(23, 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SDRAM_MBCF_AM_MODE5		PPC_REG_VAL(23, 0x5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SDRAM_MBCF_AM_MODE6		PPC_REG_VAL(23, 0x6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SDRAM_MBCF_AM_MODE7		PPC_REG_VAL(23, 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SDRAM_MBCF_AM_MODE8		PPC_REG_VAL(23, 0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SDRAM_MBCF_AM_MODE9		PPC_REG_VAL(23, 0x9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SDRAM_MBCF_BE_MASK		PPC_REG_VAL(31, 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SDRAM_MBCF_BE_DISABLE		PPC_REG_VAL(31, 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SDRAM_MBCF_BE_ENABLE		PPC_REG_VAL(31, 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)  * ECC Error Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SDRAM_ECCES_MASK		PPC_REG_VAL(21, 0x3FFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define SDRAM_ECCES_BNCE_MASK		PPC_REG_VAL(15, 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SDRAM_ECCES_BNCE_ENCODE(lane)	PPC_REG_VAL(((lane) & 0xF), 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define SDRAM_ECCES_CKBER_MASK		PPC_REG_VAL(17, 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SDRAM_ECCES_CKBER_NONE		PPC_REG_VAL(17, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SDRAM_ECCES_CKBER_16_ECC_0_3	PPC_REG_VAL(17, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SDRAM_ECCES_CKBER_32_ECC_0_3	PPC_REG_VAL(17, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SDRAM_ECCES_CKBER_32_ECC_4_8	PPC_REG_VAL(17, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SDRAM_ECCES_CKBER_32_ECC_0_8	PPC_REG_VAL(17, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define SDRAM_ECCES_CE			PPC_REG_VAL(18, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SDRAM_ECCES_UE			PPC_REG_VAL(19, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define SDRAM_ECCES_BKNER_MASK		PPC_REG_VAL(21, 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define SDRAM_ECCES_BK0ER		PPC_REG_VAL(20, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define SDRAM_ECCES_BK1ER		PPC_REG_VAL(21, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #endif /* __PPC4XX_EDAC_H */