Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Register bitfield descriptions for Pondicherry2 memory controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2016, Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #ifndef _PND2_REGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define _PND2_REGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) struct b_cr_touud_lo_pci {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 	u32	lock : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 	u32	reserved_1 : 19;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 	u32	touud : 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define b_cr_touud_lo_pci_port 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define b_cr_touud_lo_pci_offset 0xa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define b_cr_touud_lo_pci_r_opcode 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) struct b_cr_touud_hi_pci {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	u32	touud : 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	u32	reserved_0 : 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define b_cr_touud_hi_pci_port 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define b_cr_touud_hi_pci_offset 0xac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define b_cr_touud_hi_pci_r_opcode 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) struct b_cr_tolud_pci {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	u32	lock : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	u32	reserved_0 : 19;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	u32	tolud : 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define b_cr_tolud_pci_port 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define b_cr_tolud_pci_offset 0xbc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define b_cr_tolud_pci_r_opcode 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) struct b_cr_mchbar_lo_pci {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	u32 enable : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	u32 pad_3_1 : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	u32 pad_14_4: 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	u32 base: 17;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) struct b_cr_mchbar_hi_pci {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	u32 base : 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	u32 pad_31_7 : 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) /* Symmetric region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) struct b_cr_slice_channel_hash {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	u64	slice_1_disabled : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	u64	hvm_mode : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	u64	interleave_mode : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	u64	slice_0_mem_disabled : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	u64	reserved_0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	u64	slice_hash_mask : 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	u64	reserved_1 : 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	u64	enable_pmi_dual_data_mode : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	u64	ch_1_disabled : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	u64	reserved_2 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	u64	sym_slice0_channel_enabled : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	u64	sym_slice1_channel_enabled : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	u64	ch_hash_mask : 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	u64	reserved_3 : 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	u64	lock : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define b_cr_slice_channel_hash_port 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define b_cr_slice_channel_hash_offset 0x4c58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define b_cr_slice_channel_hash_r_opcode 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) struct b_cr_mot_out_base_mchbar {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	u32	reserved_0 : 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	u32	mot_out_base : 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	u32	reserved_1 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	u32	tr_en : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	u32	imr_en : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define b_cr_mot_out_base_mchbar_port 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define b_cr_mot_out_base_mchbar_offset 0x6af0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define b_cr_mot_out_base_mchbar_r_opcode 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) struct b_cr_mot_out_mask_mchbar {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	u32	reserved_0 : 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	u32	mot_out_mask : 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	u32	reserved_1 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	u32	ia_iwb_en : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	u32	gt_iwb_en : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define b_cr_mot_out_mask_mchbar_port 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define b_cr_mot_out_mask_mchbar_offset 0x6af4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define b_cr_mot_out_mask_mchbar_r_opcode 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) struct b_cr_asym_mem_region0_mchbar {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	u32	pad : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	u32	slice0_asym_base : 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	u32	pad_18_15 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	u32	slice0_asym_limit : 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	u32	slice0_asym_channel_select : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	u32	slice0_asym_enable : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define b_cr_asym_mem_region0_mchbar_port 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define b_cr_asym_mem_region0_mchbar_offset 0x6e40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define b_cr_asym_mem_region0_mchbar_r_opcode 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct b_cr_asym_mem_region1_mchbar {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	u32	pad : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	u32	slice1_asym_base : 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	u32	pad_18_15 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	u32	slice1_asym_limit : 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	u32	slice1_asym_channel_select : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	u32	slice1_asym_enable : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define b_cr_asym_mem_region1_mchbar_port 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define b_cr_asym_mem_region1_mchbar_offset 0x6e44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define b_cr_asym_mem_region1_mchbar_r_opcode 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Some bit fields moved in above two structs on Denverton */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct b_cr_asym_mem_region_denverton {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	u32	pad : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	u32	slice_asym_base : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	u32	pad_19_12 : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	u32	slice_asym_limit : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	u32	pad_28_30 : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	u32	slice_asym_enable : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct b_cr_asym_2way_mem_region_mchbar {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	u32	pad : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	u32	asym_2way_intlv_mode : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	u32	asym_2way_base : 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	u32	pad_16_15 : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	u32	asym_2way_limit : 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	u32	pad_30_28 : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	u32	asym_2way_interleave_enable : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define b_cr_asym_2way_mem_region_mchbar_port 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define b_cr_asym_2way_mem_region_mchbar_offset 0x6e50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define b_cr_asym_2way_mem_region_mchbar_r_opcode 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* Apollo Lake d-unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct d_cr_drp0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	u32	rken0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	u32	rken1 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	u32	ddmen : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	u32	rsvd3 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	u32	dwid : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	u32	dden : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	u32	rsvd13_9 : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	u32	rsien : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	u32	bahen : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	u32	rsvd18_16 : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	u32	caswizzle : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	u32	eccen : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	u32	dramtype : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	u32	blmode : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	u32	addrdec : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	u32	dramdevice_pr : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define d_cr_drp0_offset 0x1400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define d_cr_drp0_r_opcode 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* Denverton d-unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct d_cr_dsch {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	u32	ch0en : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	u32	ch1en : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	u32	ddr4en : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	u32	coldwake : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	u32	newbypdis : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	u32	chan_width : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	u32	rsvd6_6 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	u32	ooodis : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	u32	rsvd18_8 : 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	u32	ic : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	u32	rsvd31_20 : 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define d_cr_dsch_port 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define d_cr_dsch_offset 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define d_cr_dsch_r_opcode 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct d_cr_ecc_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	u32	eccen : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	u32	rsvd31_1 : 31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define d_cr_ecc_ctrl_offset 0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define d_cr_ecc_ctrl_r_opcode 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct d_cr_drp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	u32	rken0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	u32	rken1 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	u32	rken2 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	u32	rken3 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	u32	dimmdwid0 : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	u32	dimmdden0 : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	u32	dimmdwid1 : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	u32	dimmdden1 : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	u32	rsvd15_12 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	u32	dimmflip : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	u32	rsvd31_17 : 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define d_cr_drp_offset 0x158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define d_cr_drp_r_opcode 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct d_cr_dmap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	u32	ba0 : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	u32	ba1 : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	u32	bg0 : 5; /* if ddr3, ba2 = bg0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	u32	bg1 : 5; /* if ddr3, ba3 = bg1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	u32	rs0 : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	u32	rs1 : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	u32	rsvd : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define d_cr_dmap_offset 0x174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define d_cr_dmap_r_opcode 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct d_cr_dmap1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	u32	ca11 : 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	u32	bxor : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	u32	rsvd : 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define d_cr_dmap1_offset 0xb4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define d_cr_dmap1_r_opcode 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct d_cr_dmap2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	u32	row0 : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	u32	row1 : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	u32	row2 : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	u32	row3 : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	u32	row4 : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	u32	row5 : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	u32	rsvd : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define d_cr_dmap2_offset 0x148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define d_cr_dmap2_r_opcode 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct d_cr_dmap3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	u32	row6 : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	u32	row7 : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	u32	row8 : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	u32	row9 : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	u32	row10 : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	u32	row11 : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	u32	rsvd : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define d_cr_dmap3_offset 0x14c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define d_cr_dmap3_r_opcode 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct d_cr_dmap4 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	u32	row12 : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	u32	row13 : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	u32	row14 : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	u32	row15 : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	u32	row16 : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	u32	row17 : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	u32	rsvd : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define d_cr_dmap4_offset 0x150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define d_cr_dmap4_r_opcode 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct d_cr_dmap5 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	u32	ca3 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	u32	ca4 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	u32	ca5 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	u32	ca6 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	u32	ca7 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	u32	ca8 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	u32	ca9 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	u32	rsvd : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define d_cr_dmap5_offset 0x154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define d_cr_dmap5_r_opcode 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #endif /* _PND2_REGS_H */