Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2006-2007 PA Semi, Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Author: Egor Martovetsky <egor@pasemi.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Maintained by: Olof Johansson <olof@lixom.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Driver for the PWRficient onchip memory controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/pci_ids.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/edac.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include "edac_module.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define MODULE_NAME "pasemi_edac"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define MCCFG_MCEN				0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define   MCCFG_MCEN_MMC_EN			0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define MCCFG_ERRCOR				0x388
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define   MCCFG_ERRCOR_RNK_FAIL_DET_EN		0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define   MCCFG_ERRCOR_ECC_GEN_EN		0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define   MCCFG_ERRCOR_ECC_CRR_EN		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define MCCFG_SCRUB				0x384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define   MCCFG_SCRUB_RGLR_SCRB_EN		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define MCDEBUG_ERRCTL1				0x728
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define   MCDEBUG_ERRCTL1_RFL_LOG_EN		0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define   MCDEBUG_ERRCTL1_MBE_LOG_EN		0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define   MCDEBUG_ERRCTL1_SBE_LOG_EN		0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define MCDEBUG_ERRSTA				0x730
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define   MCDEBUG_ERRSTA_RFL_STATUS		0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define   MCDEBUG_ERRSTA_MBE_STATUS		0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define   MCDEBUG_ERRSTA_SBE_STATUS		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define MCDEBUG_ERRCNT1				0x734
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define   MCDEBUG_ERRCNT1_SBE_CNT_OVRFLO	0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define MCDEBUG_ERRLOG1A			0x738
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define   MCDEBUG_ERRLOG1A_MERR_TYPE_M		0x30000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define   MCDEBUG_ERRLOG1A_MERR_TYPE_NONE	0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define   MCDEBUG_ERRLOG1A_MERR_TYPE_SBE	0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define   MCDEBUG_ERRLOG1A_MERR_TYPE_MBE	0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define   MCDEBUG_ERRLOG1A_MERR_TYPE_RFL	0x30000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define   MCDEBUG_ERRLOG1A_MERR_BA_M		0x00700000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define   MCDEBUG_ERRLOG1A_MERR_BA_S		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define   MCDEBUG_ERRLOG1A_MERR_CS_M		0x00070000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define   MCDEBUG_ERRLOG1A_MERR_CS_S		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define   MCDEBUG_ERRLOG1A_SYNDROME_M		0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define MCDRAM_RANKCFG				0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define   MCDRAM_RANKCFG_EN			0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define   MCDRAM_RANKCFG_TYPE_SIZE_M		0x000001c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define   MCDRAM_RANKCFG_TYPE_SIZE_S		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define PASEMI_EDAC_NR_CSROWS			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define PASEMI_EDAC_NR_CHANS			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define PASEMI_EDAC_ERROR_GRAIN			64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static int last_page_in_mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) static int system_mmc_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) static u32 pasemi_edac_get_error_info(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	struct pci_dev *pdev = to_pci_dev(mci->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	pci_read_config_dword(pdev, MCDEBUG_ERRSTA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 			      &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	tmp &= (MCDEBUG_ERRSTA_RFL_STATUS | MCDEBUG_ERRSTA_MBE_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		| MCDEBUG_ERRSTA_SBE_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	if (tmp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		if (tmp & MCDEBUG_ERRSTA_SBE_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 			pci_write_config_dword(pdev, MCDEBUG_ERRCNT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 					       MCDEBUG_ERRCNT1_SBE_CNT_OVRFLO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		pci_write_config_dword(pdev, MCDEBUG_ERRSTA, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	return tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) static void pasemi_edac_process_error_info(struct mem_ctl_info *mci, u32 errsta)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	struct pci_dev *pdev = to_pci_dev(mci->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	u32 errlog1a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	u32 cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	if (!errsta)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	pci_read_config_dword(pdev, MCDEBUG_ERRLOG1A, &errlog1a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	cs = (errlog1a & MCDEBUG_ERRLOG1A_MERR_CS_M) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		MCDEBUG_ERRLOG1A_MERR_CS_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	/* uncorrectable/multi-bit errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	if (errsta & (MCDEBUG_ERRSTA_MBE_STATUS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		      MCDEBUG_ERRSTA_RFL_STATUS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 				     mci->csrows[cs]->first_page, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 				     cs, 0, -1, mci->ctl_name, "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	/* correctable/single-bit errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	if (errsta & MCDEBUG_ERRSTA_SBE_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 				     mci->csrows[cs]->first_page, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 				     cs, 0, -1, mci->ctl_name, "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static void pasemi_edac_check(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	u32 errsta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	errsta = pasemi_edac_get_error_info(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	if (errsta)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		pasemi_edac_process_error_info(mci, errsta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static int pasemi_edac_init_csrows(struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 				   struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 				   enum edac_type edac_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	struct csrow_info *csrow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	struct dimm_info *dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	u32 rankcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	for (index = 0; index < mci->nr_csrows; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		csrow = mci->csrows[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		dimm = csrow->channels[0]->dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		pci_read_config_dword(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 				      MCDRAM_RANKCFG + (index * 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 				      &rankcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		if (!(rankcfg & MCDRAM_RANKCFG_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		switch ((rankcfg & MCDRAM_RANKCFG_TYPE_SIZE_M) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			MCDRAM_RANKCFG_TYPE_SIZE_S) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			dimm->nr_pages = 128 << (20 - PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			dimm->nr_pages = 256 << (20 - PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 			dimm->nr_pages = 512 << (20 - PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 			dimm->nr_pages = 1024 << (20 - PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			dimm->nr_pages = 2048 << (20 - PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			edac_mc_printk(mci, KERN_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 				"Unrecognized Rank Config. rankcfg=%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 				rankcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		csrow->first_page = last_page_in_mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		csrow->last_page = csrow->first_page + dimm->nr_pages - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		last_page_in_mmc += dimm->nr_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		csrow->page_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		dimm->grain = PASEMI_EDAC_ERROR_GRAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		dimm->mtype = MEM_DDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		dimm->dtype = DEV_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		dimm->edac_mode = edac_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int pasemi_edac_probe(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 			     const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	struct mem_ctl_info *mci = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	struct edac_mc_layer layers[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	u32 errctl1, errcor, scrub, mcen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	pci_read_config_dword(pdev, MCCFG_MCEN, &mcen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	if (!(mcen & MCCFG_MCEN_MMC_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	 * We should think about enabling other error detection later on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	pci_read_config_dword(pdev, MCDEBUG_ERRCTL1, &errctl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	errctl1 |= MCDEBUG_ERRCTL1_SBE_LOG_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		MCDEBUG_ERRCTL1_MBE_LOG_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		MCDEBUG_ERRCTL1_RFL_LOG_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	pci_write_config_dword(pdev, MCDEBUG_ERRCTL1, errctl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	layers[0].size = PASEMI_EDAC_NR_CSROWS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	layers[0].is_virt_csrow = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	layers[1].type = EDAC_MC_LAYER_CHANNEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	layers[1].size = PASEMI_EDAC_NR_CHANS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	layers[1].is_virt_csrow = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	mci = edac_mc_alloc(system_mmc_id++, ARRAY_SIZE(layers), layers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 			    0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	if (mci == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	pci_read_config_dword(pdev, MCCFG_ERRCOR, &errcor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	errcor |= MCCFG_ERRCOR_RNK_FAIL_DET_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		MCCFG_ERRCOR_ECC_GEN_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		MCCFG_ERRCOR_ECC_CRR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	mci->pdev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	mci->mtype_cap = MEM_FLAG_DDR | MEM_FLAG_RDDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	mci->edac_cap = (errcor & MCCFG_ERRCOR_ECC_GEN_EN) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		((errcor & MCCFG_ERRCOR_ECC_CRR_EN) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		 (EDAC_FLAG_EC | EDAC_FLAG_SECDED) : EDAC_FLAG_EC) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		EDAC_FLAG_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	mci->mod_name = MODULE_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	mci->dev_name = pci_name(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	mci->ctl_name = "pasemi,pwrficient-mc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	mci->edac_check = pasemi_edac_check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	mci->ctl_page_to_phys = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	pci_read_config_dword(pdev, MCCFG_SCRUB, &scrub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	mci->scrub_cap = SCRUB_FLAG_HW_PROG | SCRUB_FLAG_HW_SRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	mci->scrub_mode =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		((errcor & MCCFG_ERRCOR_ECC_CRR_EN) ? SCRUB_FLAG_HW_SRC : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		((scrub & MCCFG_SCRUB_RGLR_SCRB_EN) ? SCRUB_FLAG_HW_PROG : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	if (pasemi_edac_init_csrows(mci, pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 				    (mci->edac_cap & EDAC_FLAG_SECDED) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 				    EDAC_SECDED :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 				    ((mci->edac_cap & EDAC_FLAG_EC) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 				     EDAC_EC : EDAC_NONE)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	 * Clear status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	pasemi_edac_get_error_info(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	if (edac_mc_add_mc(mci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	/* get this far and it's successful */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static void pasemi_edac_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	struct mem_ctl_info *mci = edac_mc_del_mc(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	if (!mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static const struct pci_device_id pasemi_edac_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	{ PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa00a) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) MODULE_DEVICE_TABLE(pci, pasemi_edac_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static struct pci_driver pasemi_edac_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	.name = MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	.probe = pasemi_edac_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	.remove = pasemi_edac_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	.id_table = pasemi_edac_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static int __init pasemi_edac_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)        /* Ensure that the OPSTATE is set correctly for POLL or NMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)        opstate_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	return pci_register_driver(&pasemi_edac_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static void __exit pasemi_edac_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	pci_unregister_driver(&pasemi_edac_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) module_init(pasemi_edac_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) module_exit(pasemi_edac_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) MODULE_AUTHOR("Egor Martovetsky <egor@pasemi.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) MODULE_DESCRIPTION("MC support for PA Semi PWRficient memory controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) module_param(edac_op_state, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)