Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * License.  See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2009 Wind River Systems,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *   written by Ralf Baechle <ralf@linux-mips.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Copyright (c) 2013 by Cisco Systems, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/edac.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/ctype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <asm/octeon/octeon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/octeon/cvmx-lmcx-defs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include "edac_module.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define OCTEON_MAX_MC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define to_mci(k) container_of(k, struct mem_ctl_info, dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) struct octeon_lmc_pvt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	unsigned long inject;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	unsigned long error_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	unsigned long dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	unsigned long rank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	unsigned long bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	unsigned long row;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	unsigned long col;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) static void octeon_lmc_edac_poll(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	union cvmx_lmcx_mem_cfg0 cfg0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	bool do_clear = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	char msg[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	cfg0.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(mci->mc_idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	if (cfg0.s.sec_err || cfg0.s.ded_err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		union cvmx_lmcx_fadr fadr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		fadr.u64 = cvmx_read_csr(CVMX_LMCX_FADR(mci->mc_idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		snprintf(msg, sizeof(msg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 			 "DIMM %d rank %d bank %d row %d col %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 			 fadr.cn30xx.fdimm, fadr.cn30xx.fbunk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 			 fadr.cn30xx.fbank, fadr.cn30xx.frow, fadr.cn30xx.fcol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	if (cfg0.s.sec_err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 				     -1, -1, -1, msg, "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		cfg0.s.sec_err = -1;	/* Done, re-arm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		do_clear = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	if (cfg0.s.ded_err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 				     -1, -1, -1, msg, "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		cfg0.s.ded_err = -1;	/* Done, re-arm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		do_clear = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	if (do_clear)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		cvmx_write_csr(CVMX_LMCX_MEM_CFG0(mci->mc_idx), cfg0.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) static void octeon_lmc_edac_poll_o2(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	struct octeon_lmc_pvt *pvt = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	union cvmx_lmcx_int int_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	bool do_clear = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	char msg[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	if (!pvt->inject)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		int_reg.u64 = cvmx_read_csr(CVMX_LMCX_INT(mci->mc_idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		int_reg.u64 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		if (pvt->error_type == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 			int_reg.s.sec_err = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		if (pvt->error_type == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 			int_reg.s.ded_err = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	if (int_reg.s.sec_err || int_reg.s.ded_err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		union cvmx_lmcx_fadr fadr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		if (likely(!pvt->inject))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 			fadr.u64 = cvmx_read_csr(CVMX_LMCX_FADR(mci->mc_idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 			fadr.cn61xx.fdimm = pvt->dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 			fadr.cn61xx.fbunk = pvt->rank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 			fadr.cn61xx.fbank = pvt->bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 			fadr.cn61xx.frow = pvt->row;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 			fadr.cn61xx.fcol = pvt->col;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		snprintf(msg, sizeof(msg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 			 "DIMM %d rank %d bank %d row %d col %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 			 fadr.cn61xx.fdimm, fadr.cn61xx.fbunk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 			 fadr.cn61xx.fbank, fadr.cn61xx.frow, fadr.cn61xx.fcol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	if (int_reg.s.sec_err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 				     -1, -1, -1, msg, "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		int_reg.s.sec_err = -1;	/* Done, re-arm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		do_clear = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	if (int_reg.s.ded_err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 				     -1, -1, -1, msg, "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		int_reg.s.ded_err = -1;	/* Done, re-arm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		do_clear = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	if (do_clear) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		if (likely(!pvt->inject))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 			cvmx_write_csr(CVMX_LMCX_INT(mci->mc_idx), int_reg.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			pvt->inject = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /************************ MC SYSFS parts ***********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* Only a couple naming differences per template, so very similar */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define TEMPLATE_SHOW(reg)						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static ssize_t octeon_mc_inject_##reg##_show(struct device *dev,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			       struct device_attribute *attr,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 			       char *data)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {									\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	struct mem_ctl_info *mci = to_mci(dev);				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	struct octeon_lmc_pvt *pvt = mci->pvt_info;			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	return sprintf(data, "%016llu\n", (u64)pvt->reg);		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define TEMPLATE_STORE(reg)						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static ssize_t octeon_mc_inject_##reg##_store(struct device *dev,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			       struct device_attribute *attr,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			       const char *data, size_t count)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {									\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	struct mem_ctl_info *mci = to_mci(dev);				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	struct octeon_lmc_pvt *pvt = mci->pvt_info;			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	if (isdigit(*data)) {						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		if (!kstrtoul(data, 0, &pvt->reg))			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 			return count;					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	}								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	return 0;							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) TEMPLATE_SHOW(inject);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) TEMPLATE_STORE(inject);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) TEMPLATE_SHOW(dimm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) TEMPLATE_STORE(dimm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) TEMPLATE_SHOW(bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) TEMPLATE_STORE(bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) TEMPLATE_SHOW(rank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) TEMPLATE_STORE(rank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) TEMPLATE_SHOW(row);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) TEMPLATE_STORE(row);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) TEMPLATE_SHOW(col);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) TEMPLATE_STORE(col);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static ssize_t octeon_mc_inject_error_type_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 					  struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 					  const char *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 					  size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	struct mem_ctl_info *mci = to_mci(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	struct octeon_lmc_pvt *pvt = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	if (!strncmp(data, "single", 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		pvt->error_type = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	else if (!strncmp(data, "double", 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		pvt->error_type = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static ssize_t octeon_mc_inject_error_type_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 					 struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 					 char *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	struct mem_ctl_info *mci = to_mci(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	struct octeon_lmc_pvt *pvt = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	if (pvt->error_type == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		return sprintf(data, "single");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	else if (pvt->error_type == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		return sprintf(data, "double");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static DEVICE_ATTR(inject, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		   octeon_mc_inject_inject_show, octeon_mc_inject_inject_store);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static DEVICE_ATTR(error_type, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		   octeon_mc_inject_error_type_show, octeon_mc_inject_error_type_store);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static DEVICE_ATTR(dimm, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		   octeon_mc_inject_dimm_show, octeon_mc_inject_dimm_store);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static DEVICE_ATTR(rank, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		   octeon_mc_inject_rank_show, octeon_mc_inject_rank_store);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static DEVICE_ATTR(bank, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		   octeon_mc_inject_bank_show, octeon_mc_inject_bank_store);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static DEVICE_ATTR(row, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		   octeon_mc_inject_row_show, octeon_mc_inject_row_store);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static DEVICE_ATTR(col, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		   octeon_mc_inject_col_show, octeon_mc_inject_col_store);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static struct attribute *octeon_dev_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	&dev_attr_inject.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	&dev_attr_error_type.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	&dev_attr_dimm.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	&dev_attr_rank.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	&dev_attr_bank.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	&dev_attr_row.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	&dev_attr_col.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ATTRIBUTE_GROUPS(octeon_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static int octeon_lmc_edac_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	struct mem_ctl_info *mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	struct edac_mc_layer layers[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	int mc = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	opstate_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	layers[0].type = EDAC_MC_LAYER_CHANNEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	layers[0].size = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	layers[0].is_virt_csrow = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	if (OCTEON_IS_OCTEON1PLUS()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		union cvmx_lmcx_mem_cfg0 cfg0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		cfg0.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		if (!cfg0.s.ecc_ena) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 			dev_info(&pdev->dev, "Disabled (ECC not enabled)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers, sizeof(struct octeon_lmc_pvt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		if (!mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 			return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		mci->pdev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		mci->dev_name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		mci->mod_name = "octeon-lmc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		mci->ctl_name = "octeon-lmc-err";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		mci->edac_check = octeon_lmc_edac_poll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		if (edac_mc_add_mc_with_groups(mci, octeon_dev_groups)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 			dev_err(&pdev->dev, "edac_mc_add_mc() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 			edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 			return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		cfg0.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(mc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		cfg0.s.intr_ded_ena = 0;	/* We poll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		cfg0.s.intr_sec_ena = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		cvmx_write_csr(CVMX_LMCX_MEM_CFG0(mc), cfg0.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		/* OCTEON II */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		union cvmx_lmcx_int_en en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		union cvmx_lmcx_config config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		config.u64 = cvmx_read_csr(CVMX_LMCX_CONFIG(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		if (!config.s.ecc_ena) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 			dev_info(&pdev->dev, "Disabled (ECC not enabled)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers, sizeof(struct octeon_lmc_pvt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		if (!mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 			return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		mci->pdev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		mci->dev_name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		mci->mod_name = "octeon-lmc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		mci->ctl_name = "co_lmc_err";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		mci->edac_check = octeon_lmc_edac_poll_o2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		if (edac_mc_add_mc_with_groups(mci, octeon_dev_groups)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 			dev_err(&pdev->dev, "edac_mc_add_mc() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 			edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 			return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		en.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(mc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		en.s.intr_ded_ena = 0;	/* We poll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		en.s.intr_sec_ena = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		cvmx_write_csr(CVMX_LMCX_MEM_CFG0(mc), en.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	platform_set_drvdata(pdev, mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static int octeon_lmc_edac_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	struct mem_ctl_info *mci = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	edac_mc_del_mc(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static struct platform_driver octeon_lmc_edac_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	.probe = octeon_lmc_edac_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	.remove = octeon_lmc_edac_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		   .name = "octeon_lmc_edac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) module_platform_driver(octeon_lmc_edac_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");