^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * EDAC defs for Marvell MV64x60 bridge chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Dave Jiang <djiang@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * 2007 (c) MontaVista Software, Inc. This file is licensed under
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * the terms of the GNU General Public License version 2. This program
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * is licensed "as is" without any warranty of any kind, whether express
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef _MV64X60_EDAC_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define _MV64X60_EDAC_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MV64x60_REVISION " Ver: 2.0.0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define EDAC_MOD_STR "MV64x60_edac"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define mv64x60_printk(level, fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) edac_printk(level, "MV64x60", fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define mv64x60_mc_printk(mci, level, fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) edac_mc_chipset_printk(mci, level, "MV64x60", fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* CPU Error Report Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MV64x60_CPU_ERR_ADDR_LO 0x00 /* 0x0070 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MV64x60_CPU_ERR_ADDR_HI 0x08 /* 0x0078 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MV64x60_CPU_ERR_DATA_LO 0x00 /* 0x0128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MV64x60_CPU_ERR_DATA_HI 0x08 /* 0x0130 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MV64x60_CPU_ERR_PARITY 0x10 /* 0x0138 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MV64x60_CPU_ERR_CAUSE 0x18 /* 0x0140 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MV64x60_CPU_ERR_MASK 0x20 /* 0x0148 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MV64x60_CPU_CAUSE_MASK 0x07ffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* SRAM Error Report Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MV64X60_SRAM_ERR_CAUSE 0x08 /* 0x0388 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MV64X60_SRAM_ERR_ADDR_LO 0x10 /* 0x0390 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MV64X60_SRAM_ERR_ADDR_HI 0x78 /* 0x03f8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MV64X60_SRAM_ERR_DATA_LO 0x18 /* 0x0398 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MV64X60_SRAM_ERR_DATA_HI 0x20 /* 0x03a0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MV64X60_SRAM_ERR_PARITY 0x28 /* 0x03a8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* SDRAM Controller Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MV64X60_SDRAM_CONFIG 0x00 /* 0x1400 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MV64X60_SDRAM_ERR_DATA_HI 0x40 /* 0x1440 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MV64X60_SDRAM_ERR_DATA_LO 0x44 /* 0x1444 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MV64X60_SDRAM_ERR_ECC_RCVD 0x48 /* 0x1448 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MV64X60_SDRAM_ERR_ECC_CALC 0x4c /* 0x144c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MV64X60_SDRAM_ERR_ADDR 0x50 /* 0x1450 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MV64X60_SDRAM_ERR_ECC_CNTL 0x54 /* 0x1454 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MV64X60_SDRAM_ERR_ECC_ERR_CNT 0x58 /* 0x1458 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MV64X60_SDRAM_REGISTERED 0x20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MV64X60_SDRAM_ECC 0x40000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * Bit 0 of MV64x60_PCIx_ERR_MASK does not exist on the 64360 and because of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * errata FEr-#11 and FEr-##16 for the 64460, it should be 0 on that chip as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * well. IOW, don't set bit 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MV64X60_PCIx_ERR_MASK_VAL 0x00a50c24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* Register offsets from PCIx error address low register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MV64X60_PCI_ERROR_ADDR_LO 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MV64X60_PCI_ERROR_ADDR_HI 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MV64X60_PCI_ERROR_ATTR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MV64X60_PCI_ERROR_CMD 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MV64X60_PCI_ERROR_CAUSE 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MV64X60_PCI_ERROR_MASK 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MV64X60_PCI_ERR_SWrPerr 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MV64X60_PCI_ERR_SRdPerr 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MV64X60_PCI_ERR_MWrPerr 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MV64X60_PCI_ERR_MRdPerr 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MV64X60_PCI_PE_MASK (MV64X60_PCI_ERR_SWrPerr | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) MV64X60_PCI_ERR_SRdPerr | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MV64X60_PCI_ERR_MWrPerr | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MV64X60_PCI_ERR_MRdPerr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct mv64x60_pci_pdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int pci_hose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) void __iomem *pci_vbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) int edac_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #endif /* CONFIG_PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct mv64x60_mc_pdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) void __iomem *mc_vbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int total_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int edac_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct mv64x60_cpu_pdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) void __iomem *cpu_vbase[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int edac_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct mv64x60_sram_pdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) void __iomem *sram_vbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int edac_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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