^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Freescale MPC85xx Memory Controller kernel module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Author: Dave Jiang <djiang@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * the terms of the GNU General Public License version 2. This program
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * is licensed "as is" without any warranty of any kind, whether express
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef _MPC85XX_EDAC_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define _MPC85XX_EDAC_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MPC85XX_REVISION " Ver: 2.0.0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define EDAC_MOD_STR "MPC85xx_edac"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define mpc85xx_printk(level, fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) edac_printk(level, "MPC85xx", fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * L2 Err defines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MPC85XX_L2_ERRINJHI 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MPC85XX_L2_ERRINJLO 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MPC85XX_L2_ERRINJCTL 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MPC85XX_L2_CAPTDATAHI 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MPC85XX_L2_CAPTDATALO 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MPC85XX_L2_CAPTECC 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MPC85XX_L2_ERRDET 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MPC85XX_L2_ERRDIS 0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MPC85XX_L2_ERRINTEN 0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MPC85XX_L2_ERRATTR 0x004c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MPC85XX_L2_ERRADDR 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MPC85XX_L2_ERRCTL 0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* Error Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define L2_EIE_L2CFGINTEN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define L2_EIE_SBECCINTEN 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define L2_EIE_MBECCINTEN 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define L2_EIE_TPARINTEN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define L2_EIE_MASK (L2_EIE_L2CFGINTEN | L2_EIE_SBECCINTEN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) L2_EIE_MBECCINTEN | L2_EIE_TPARINTEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Error Detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define L2_EDE_L2CFGERR 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define L2_EDE_SBECCERR 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define L2_EDE_MBECCERR 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define L2_EDE_TPARERR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define L2_EDE_MULL2ERR 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define L2_EDE_CE_MASK L2_EDE_SBECCERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define L2_EDE_UE_MASK (L2_EDE_L2CFGERR | L2_EDE_MBECCERR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) L2_EDE_TPARERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define L2_EDE_MASK (L2_EDE_L2CFGERR | L2_EDE_SBECCERR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) L2_EDE_MBECCERR | L2_EDE_TPARERR | L2_EDE_MULL2ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * PCI Err defines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PCI_EDE_TOE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PCI_EDE_SCM 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PCI_EDE_IRMSV 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PCI_EDE_ORMSV 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PCI_EDE_OWMSV 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PCI_EDE_TGT_ABRT 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PCI_EDE_MST_ABRT 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PCI_EDE_TGT_PERR 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PCI_EDE_MST_PERR 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PCI_EDE_RCVD_SERR 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PCI_EDE_ADDR_PERR 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PCI_EDE_MULTI_ERR 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PCI_EDE_PERR_MASK (PCI_EDE_TGT_PERR | PCI_EDE_MST_PERR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) PCI_EDE_ADDR_PERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MPC85XX_PCI_ERR_DR 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MPC85XX_PCI_ERR_CAP_DR 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MPC85XX_PCI_ERR_EN 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PEX_ERR_ICCAIE_EN_BIT 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MPC85XX_PCI_ERR_ATTRIB 0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MPC85XX_PCI_ERR_ADDR 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PEX_ERR_ICCAD_DISR_BIT 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MPC85XX_PCI_ERR_EXT_ADDR 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MPC85XX_PCI_ERR_DL 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MPC85XX_PCI_ERR_DH 0x001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MPC85XX_PCI_GAS_TIMR 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MPC85XX_PCI_PCIX_TIMR 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MPC85XX_PCIE_ERR_CAP_R0 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MPC85XX_PCIE_ERR_CAP_R1 0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MPC85XX_PCIE_ERR_CAP_R2 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MPC85XX_PCIE_ERR_CAP_R3 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct mpc85xx_l2_pdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int edac_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) void __iomem *l2_vbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct mpc85xx_pci_pdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) bool is_pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int edac_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) void __iomem *pci_vbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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