Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #ifndef _EDAC_MCE_AMD_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #define _EDAC_MCE_AMD_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #include <linux/notifier.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <asm/mce.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define EC(x)				((x) & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define LOW_SYNDROME(x)			(((x) >> 15) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define HIGH_SYNDROME(x)		(((x) >> 24) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define TLB_ERROR(x)			(((x) & 0xFFF0) == 0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MEM_ERROR(x)			(((x) & 0xFF00) == 0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define BUS_ERROR(x)			(((x) & 0xF800) == 0x0800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define INT_ERROR(x)			(((x) & 0xF4FF) == 0x0400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TT(x)				(((x) >> 2) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TT_MSG(x)			tt_msgs[TT(x)]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define II(x)				(((x) >> 2) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define II_MSG(x)			ii_msgs[II(x)]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define LL(x)				((x) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define LL_MSG(x)			ll_msgs[LL(x)]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TO(x)				(((x) >> 8) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TO_MSG(x)			to_msgs[TO(x)]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PP(x)				(((x) >> 9) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PP_MSG(x)			pp_msgs[PP(x)]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define UU(x)				(((x) >> 8) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define UU_MSG(x)			uu_msgs[UU(x)]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define R4(x)				(((x) >> 4) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define R4_MSG(x)			((R4(x) < 9) ?  rrrr_msgs[R4(x)] : "Wrong R4!")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) extern const char * const pp_msgs[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) enum tt_ids {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	TT_INSTR = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	TT_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	TT_GEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	TT_RESV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) enum ll_ids {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	LL_RESV = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	LL_L1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	LL_L2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	LL_LG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) enum ii_ids {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	II_MEM = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	II_RESV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	II_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	II_GEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) enum rrrr_ids {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	R4_GEN	= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	R4_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	R4_WR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	R4_DRD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	R4_DWR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	R4_IRD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	R4_PREF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	R4_EVICT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	R4_SNOOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)  * per-family decoder ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct amd_decoder_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	bool (*mc0_mce)(u16, u8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 	bool (*mc1_mce)(u16, u8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 	bool (*mc2_mce)(u16, u8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) void amd_register_ecc_decoder(void (*f)(int, struct mce *));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) void amd_unregister_ecc_decoder(void (*f)(int, struct mce *));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #endif /* _EDAC_MCE_AMD_H */