^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <asm/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include "mce_amd.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) static struct amd_decoder_ops fam_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) static u8 xec_mask = 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) static void (*decode_dram_ecc)(int node_id, struct mce *m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) void amd_register_ecc_decoder(void (*f)(int, struct mce *))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) decode_dram_ecc = f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) EXPORT_SYMBOL_GPL(amd_register_ecc_decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) void amd_unregister_ecc_decoder(void (*f)(int, struct mce *))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) if (decode_dram_ecc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) WARN_ON(decode_dram_ecc != f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) decode_dram_ecc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) EXPORT_SYMBOL_GPL(amd_unregister_ecc_decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * string representation for the different MCA reported error types, see F3x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * or MSR0000_0411.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* transaction type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static const char * const tt_msgs[] = { "INSN", "DATA", "GEN", "RESV" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* cache level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static const char * const ll_msgs[] = { "RESV", "L1", "L2", "L3/GEN" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* memory transaction type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static const char * const rrrr_msgs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) "GEN", "RD", "WR", "DRD", "DWR", "IRD", "PRF", "EV", "SNP"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* participating processor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) const char * const pp_msgs[] = { "SRC", "RES", "OBS", "GEN" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) EXPORT_SYMBOL_GPL(pp_msgs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* request timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static const char * const to_msgs[] = { "no timeout", "timed out" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* memory or i/o */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static const char * const ii_msgs[] = { "MEM", "RESV", "IO", "GEN" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* internal error type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static const char * const uu_msgs[] = { "RESV", "RESV", "HWA", "RESV" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static const char * const f15h_mc1_mce_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) "UC during a demand linefill from L2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) "Parity error during data load from IC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) "Parity error for IC valid bit",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) "Main tag parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) "Parity error in prediction queue",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) "PFB data/address parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) "Parity error in the branch status reg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) "PFB promotion address error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) "Tag error during probe/victimization",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) "Parity error for IC probe tag valid bit",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) "PFB non-cacheable bit parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) "PFB valid bit parity error", /* xec = 0xd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) "Microcode Patch Buffer", /* xec = 010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) "uop queue",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) "insn buffer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) "predecode buffer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) "fetch address FIFO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) "dispatch uop queue"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static const char * const f15h_mc2_mce_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) "Fill ECC error on data fills", /* xec = 0x4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) "Fill parity error on insn fills",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) "Prefetcher request FIFO parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) "PRQ address parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) "PRQ data parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) "WCC Tag ECC error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) "WCC Data ECC error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) "WCB Data parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) "VB Data ECC or parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) "L2 Tag ECC error", /* xec = 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) "Hard L2 Tag ECC error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) "Multiple hits on L2 tag",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) "XAB parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) "PRB address parity error"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static const char * const mc4_mce_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) "DRAM ECC error detected on the NB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) "CRC error detected on HT link",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) "Link-defined sync error packets detected on HT link",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) "HT Master abort",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) "HT Target abort",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) "Invalid GART PTE entry during GART table walk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) "Unsupported atomic RMW received from an IO link",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) "Watchdog timeout due to lack of progress",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) "DRAM ECC error detected on the NB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) "SVM DMA Exclusion Vector error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) "HT data error detected on link",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) "Protocol error (link, L3, probe filter)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) "NB internal arrays parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) "DRAM addr/ctl signals parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) "IO link transmission error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) "L3 data cache ECC error", /* xec = 0x1c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) "L3 cache tag error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) "L3 LRU parity bits error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) "ECC Error in the Probe Filter directory"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static const char * const mc5_mce_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) "CPU Watchdog timer expire",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) "Wakeup array dest tag",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) "AG payload array",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) "EX payload array",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) "IDRF array",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) "Retire dispatch queue",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) "Mapper checkpoint array",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) "Physical register file EX0 port",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) "Physical register file EX1 port",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) "Physical register file AG0 port",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) "Physical register file AG1 port",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) "Flag register file",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) "DE error occurred",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) "Retire status queue"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static const char * const mc6_mce_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) "Hardware Assertion",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) "Free List",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) "Physical Register File",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) "Retire Queue",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) "Scheduler table",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) "Status Register File",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Scalable MCA error strings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static const char * const smca_ls_mce_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) "Load queue parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) "Store queue parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) "Miss address buffer payload parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) "Level 1 TLB parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) "DC Tag error type 5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) "DC Tag error type 6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) "DC Tag error type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) "Internal error type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) "Internal error type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) "System Read Data Error Thread 0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) "System Read Data Error Thread 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) "DC Tag error type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) "DC Data error type 1 and poison consumption",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) "DC Data error type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) "DC Data error type 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) "DC Tag error type 4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) "Level 2 TLB parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) "PDC parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) "DC Tag error type 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) "DC Tag error type 5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) "L2 Fill Data error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static const char * const smca_ls2_mce_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) "An ECC error was detected on a data cache read by a probe or victimization",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) "An ECC error or L2 poison was detected on a data cache read by a load",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) "An ECC error was detected on a data cache read-modify-write by a store",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) "An ECC error or poison bit mismatch was detected on a tag read by a probe or victimization",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) "An ECC error or poison bit mismatch was detected on a tag read by a load",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) "An ECC error or poison bit mismatch was detected on a tag read by a store",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) "An ECC error was detected on an EMEM read by a load",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) "An ECC error was detected on an EMEM read-modify-write by a store",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) "A parity error was detected in an L1 TLB entry by any access",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) "A parity error was detected in an L2 TLB entry by any access",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) "A parity error was detected in a PWC entry by any access",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) "A parity error was detected in an STQ entry by any access",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) "A parity error was detected in an LDQ entry by any access",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) "A parity error was detected in a MAB entry by any access",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) "A parity error was detected in an SCB entry state field by any access",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) "A parity error was detected in an SCB entry address field by any access",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) "A parity error was detected in an SCB entry data field by any access",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) "A parity error was detected in a WCB entry by any access",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) "A poisoned line was detected in an SCB entry by any access",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) "A SystemReadDataError error was reported on read data returned from L2 for a load",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) "A SystemReadDataError error was reported on read data returned from L2 for an SCB store",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) "A SystemReadDataError error was reported on read data returned from L2 for a WCB store",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) "A hardware assertion error was reported",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) "A parity error was detected in an STLF, SCB EMEM entry or SRB store data by any access",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static const char * const smca_if_mce_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) "Op Cache Microtag Probe Port Parity Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) "IC Microtag or Full Tag Multi-hit Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) "IC Full Tag Parity Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) "IC Data Array Parity Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) "Decoupling Queue PhysAddr Parity Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) "L0 ITLB Parity Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) "L1 ITLB Parity Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) "L2 ITLB Parity Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) "BPQ Thread 0 Snoop Parity Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) "BPQ Thread 1 Snoop Parity Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) "L1 BTB Multi-Match Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) "L2 BTB Multi-Match Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) "L2 Cache Response Poison Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) "System Read Data Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) "Hardware Assertion Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) "L1-TLB Multi-Hit",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) "L2-TLB Multi-Hit",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) "BSR Parity Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) "CT MCE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static const char * const smca_l2_mce_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) "L2M Tag Multiple-Way-Hit error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) "L2M Tag or State Array ECC Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) "L2M Data Array ECC Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) "Hardware Assert Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static const char * const smca_de_mce_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) "Micro-op cache tag parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) "Micro-op cache data parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) "Instruction buffer parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) "Micro-op queue parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) "Instruction dispatch queue parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) "Fetch address FIFO parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) "Patch RAM data parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) "Patch RAM sequencer parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) "Micro-op buffer parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) "Hardware Assertion MCA Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static const char * const smca_ex_mce_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) "Watchdog Timeout error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) "Physical register file parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) "Flag register file parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) "Immediate displacement register file parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) "Address generator payload parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) "EX payload parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) "Checkpoint queue parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) "Retire dispatch queue parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) "Retire status queue parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) "Scheduling queue parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) "Branch buffer queue parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) "Hardware Assertion error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) "Spec Map parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) "Retire Map parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static const char * const smca_fp_mce_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) "Physical register file (PRF) parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) "Freelist (FL) parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) "Schedule queue parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) "NSQ parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) "Retire queue (RQ) parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) "Status register file (SRF) parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) "Hardware assertion",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static const char * const smca_l3_mce_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) "Shadow Tag Macro ECC Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) "Shadow Tag Macro Multi-way-hit Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) "L3M Tag ECC Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) "L3M Tag Multi-way-hit Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) "L3M Data ECC Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) "SDP Parity Error or SystemReadDataError from XI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) "L3 Victim Queue Parity Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) "L3 Hardware Assertion",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static const char * const smca_cs_mce_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) "Illegal Request",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) "Address Violation",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) "Security Violation",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) "Illegal Response",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) "Unexpected Response",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) "Request or Probe Parity Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) "Read Response Parity Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) "Atomic Request Parity Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) "Probe Filter ECC Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static const char * const smca_cs2_mce_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) "Illegal Request",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) "Address Violation",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) "Security Violation",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) "Illegal Response",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) "Unexpected Response",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) "Request or Probe Parity Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) "Read Response Parity Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) "Atomic Request Parity Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) "SDP read response had no match in the CS queue",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) "Probe Filter Protocol Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) "Probe Filter ECC Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) "SDP read response had an unexpected RETRY error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) "Counter overflow error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) "Counter underflow error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static const char * const smca_pie_mce_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) "Hardware Assert",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) "Register security violation",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) "Link Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) "Poison data consumption",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) "A deferred error was detected in the DF"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static const char * const smca_umc_mce_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) "DRAM ECC error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) "Data poison error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) "SDP parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) "Advanced peripheral bus error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) "Address/Command parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) "Write data CRC error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) "DCQ SRAM ECC error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) "AES SRAM ECC error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static const char * const smca_pb_mce_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) "An ECC error in the Parameter Block RAM array",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static const char * const smca_psp_mce_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) "An ECC or parity error in a PSP RAM instance",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static const char * const smca_psp2_mce_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) "High SRAM ECC or parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) "Low SRAM ECC or parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) "Instruction Cache Bank 0 ECC or parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) "Instruction Cache Bank 1 ECC or parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) "Instruction Tag Ram 0 parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) "Instruction Tag Ram 1 parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) "Data Cache Bank 0 ECC or parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) "Data Cache Bank 1 ECC or parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) "Data Cache Bank 2 ECC or parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) "Data Cache Bank 3 ECC or parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) "Data Tag Bank 0 parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) "Data Tag Bank 1 parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) "Data Tag Bank 2 parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) "Data Tag Bank 3 parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) "Dirty Data Ram parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) "TLB Bank 0 parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) "TLB Bank 1 parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) "System Hub Read Buffer ECC or parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static const char * const smca_smu_mce_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) "An ECC or parity error in an SMU RAM instance",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static const char * const smca_smu2_mce_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) "High SRAM ECC or parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) "Low SRAM ECC or parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) "Data Cache Bank A ECC or parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) "Data Cache Bank B ECC or parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) "Data Tag Cache Bank A ECC or parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) "Data Tag Cache Bank B ECC or parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) "Instruction Cache Bank A ECC or parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) "Instruction Cache Bank B ECC or parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) "Instruction Tag Cache Bank A ECC or parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) "Instruction Tag Cache Bank B ECC or parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) "System Hub Read Buffer ECC or parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) "PHY RAM ECC error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static const char * const smca_mp5_mce_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) "High SRAM ECC or parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) "Low SRAM ECC or parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) "Data Cache Bank A ECC or parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) "Data Cache Bank B ECC or parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) "Data Tag Cache Bank A ECC or parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) "Data Tag Cache Bank B ECC or parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) "Instruction Cache Bank A ECC or parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) "Instruction Cache Bank B ECC or parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) "Instruction Tag Cache Bank A ECC or parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) "Instruction Tag Cache Bank B ECC or parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static const char * const smca_nbio_mce_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) "ECC or Parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) "PCIE error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) "SDP ErrEvent error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) "SDP Egress Poison Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) "IOHC Internal Poison Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static const char * const smca_pcie_mce_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) "CCIX PER Message logging",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) "CCIX Read Response with Status: Non-Data Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) "CCIX Write Response with Status: Non-Data Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) "CCIX Read Response with Status: Data Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) "CCIX Non-okay write response with data error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct smca_mce_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) const char * const *descs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) unsigned int num_descs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static struct smca_mce_desc smca_mce_descs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) [SMCA_LS] = { smca_ls_mce_desc, ARRAY_SIZE(smca_ls_mce_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) [SMCA_LS_V2] = { smca_ls2_mce_desc, ARRAY_SIZE(smca_ls2_mce_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) [SMCA_IF] = { smca_if_mce_desc, ARRAY_SIZE(smca_if_mce_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) [SMCA_L2_CACHE] = { smca_l2_mce_desc, ARRAY_SIZE(smca_l2_mce_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) [SMCA_DE] = { smca_de_mce_desc, ARRAY_SIZE(smca_de_mce_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) [SMCA_EX] = { smca_ex_mce_desc, ARRAY_SIZE(smca_ex_mce_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) [SMCA_FP] = { smca_fp_mce_desc, ARRAY_SIZE(smca_fp_mce_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) [SMCA_L3_CACHE] = { smca_l3_mce_desc, ARRAY_SIZE(smca_l3_mce_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) [SMCA_CS] = { smca_cs_mce_desc, ARRAY_SIZE(smca_cs_mce_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) [SMCA_CS_V2] = { smca_cs2_mce_desc, ARRAY_SIZE(smca_cs2_mce_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) [SMCA_PIE] = { smca_pie_mce_desc, ARRAY_SIZE(smca_pie_mce_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) [SMCA_UMC] = { smca_umc_mce_desc, ARRAY_SIZE(smca_umc_mce_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) [SMCA_PB] = { smca_pb_mce_desc, ARRAY_SIZE(smca_pb_mce_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) [SMCA_PSP] = { smca_psp_mce_desc, ARRAY_SIZE(smca_psp_mce_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) [SMCA_PSP_V2] = { smca_psp2_mce_desc, ARRAY_SIZE(smca_psp2_mce_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) [SMCA_SMU] = { smca_smu_mce_desc, ARRAY_SIZE(smca_smu_mce_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) [SMCA_SMU_V2] = { smca_smu2_mce_desc, ARRAY_SIZE(smca_smu2_mce_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) [SMCA_MP5] = { smca_mp5_mce_desc, ARRAY_SIZE(smca_mp5_mce_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) [SMCA_NBIO] = { smca_nbio_mce_desc, ARRAY_SIZE(smca_nbio_mce_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) [SMCA_PCIE] = { smca_pcie_mce_desc, ARRAY_SIZE(smca_pcie_mce_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static bool f12h_mc0_mce(u16 ec, u8 xec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) bool ret = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (MEM_ERROR(ec)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) u8 ll = LL(ec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) ret = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (ll == LL_L2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) pr_cont("during L1 linefill from L2.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) else if (ll == LL_L1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) pr_cont("Data/Tag %s error.\n", R4_MSG(ec));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) ret = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static bool f10h_mc0_mce(u16 ec, u8 xec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (R4(ec) == R4_GEN && LL(ec) == LL_L1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) pr_cont("during data scrub.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return f12h_mc0_mce(ec, xec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static bool k8_mc0_mce(u16 ec, u8 xec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (BUS_ERROR(ec)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) pr_cont("during system linefill.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return f10h_mc0_mce(ec, xec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static bool cat_mc0_mce(u16 ec, u8 xec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) u8 r4 = R4(ec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) bool ret = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (MEM_ERROR(ec)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (TT(ec) != TT_DATA || LL(ec) != LL_L1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) switch (r4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) case R4_DRD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) case R4_DWR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) pr_cont("Data/Tag parity error due to %s.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) (r4 == R4_DRD ? "load/hw prf" : "store"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) case R4_EVICT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) pr_cont("Copyback parity error on a tag miss.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) case R4_SNOOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) pr_cont("Tag parity error during snoop.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) ret = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) } else if (BUS_ERROR(ec)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if ((II(ec) != II_MEM && II(ec) != II_IO) || LL(ec) != LL_LG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) pr_cont("System read data error on a ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) switch (r4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) case R4_RD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) pr_cont("TLB reload.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) case R4_DWR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) pr_cont("store.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) case R4_DRD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) pr_cont("load.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) ret = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) ret = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static bool f15h_mc0_mce(u16 ec, u8 xec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) bool ret = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (MEM_ERROR(ec)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) switch (xec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) case 0x0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) pr_cont("Data Array access error.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) case 0x1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) pr_cont("UC error during a linefill from L2/NB.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) case 0x2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) case 0x11:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) pr_cont("STQ access error.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) case 0x3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) pr_cont("SCB access error.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) case 0x10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) pr_cont("Tag error.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) case 0x12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) pr_cont("LDQ access error.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) ret = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) } else if (BUS_ERROR(ec)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (!xec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) pr_cont("System Read Data Error.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) pr_cont(" Internal error condition type %d.\n", xec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) } else if (INT_ERROR(ec)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (xec <= 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) pr_cont("Hardware Assert.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) ret = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ret = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static void decode_mc0_mce(struct mce *m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) u16 ec = EC(m->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) u8 xec = XEC(m->status, xec_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) pr_emerg(HW_ERR "MC0 Error: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /* TLB error signatures are the same across families */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (TLB_ERROR(ec)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (TT(ec) == TT_DATA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) pr_cont("%s TLB %s.\n", LL_MSG(ec),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) ((xec == 2) ? "locked miss"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) : (xec ? "multimatch" : "parity")));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) } else if (fam_ops.mc0_mce(ec, xec))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) pr_emerg(HW_ERR "Corrupted MC0 MCE info?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static bool k8_mc1_mce(u16 ec, u8 xec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) u8 ll = LL(ec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) bool ret = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (!MEM_ERROR(ec))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (ll == 0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) pr_cont("during a linefill from L2.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) else if (ll == 0x1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) switch (R4(ec)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) case R4_IRD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) pr_cont("Parity error during data load.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) case R4_EVICT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) pr_cont("Copyback Parity/Victim error.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) case R4_SNOOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) pr_cont("Tag Snoop error.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) ret = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) ret = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static bool cat_mc1_mce(u16 ec, u8 xec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) u8 r4 = R4(ec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) bool ret = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (!MEM_ERROR(ec))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (TT(ec) != TT_INSTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (r4 == R4_IRD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) pr_cont("Data/tag array parity error for a tag hit.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) else if (r4 == R4_SNOOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) pr_cont("Tag error during snoop/victimization.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) else if (xec == 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) pr_cont("Tag parity error from victim castout.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) else if (xec == 0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) pr_cont("Microcode patch RAM parity error.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) ret = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static bool f15h_mc1_mce(u16 ec, u8 xec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) bool ret = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (!MEM_ERROR(ec))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) switch (xec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) case 0x0 ... 0xa:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) pr_cont("%s.\n", f15h_mc1_mce_desc[xec]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) case 0xd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) pr_cont("%s.\n", f15h_mc1_mce_desc[xec-2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) case 0x10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) pr_cont("%s.\n", f15h_mc1_mce_desc[xec-4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) case 0x11 ... 0x15:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) pr_cont("Decoder %s parity error.\n", f15h_mc1_mce_desc[xec-4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) ret = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) static void decode_mc1_mce(struct mce *m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) u16 ec = EC(m->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) u8 xec = XEC(m->status, xec_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) pr_emerg(HW_ERR "MC1 Error: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (TLB_ERROR(ec))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) pr_cont("%s TLB %s.\n", LL_MSG(ec),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) (xec ? "multimatch" : "parity error"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) else if (BUS_ERROR(ec)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) bool k8 = (boot_cpu_data.x86 == 0xf && (m->status & BIT_64(58)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) pr_cont("during %s.\n", (k8 ? "system linefill" : "NB data read"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) } else if (INT_ERROR(ec)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (xec <= 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) pr_cont("Hardware Assert.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) goto wrong_mc1_mce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) } else if (fam_ops.mc1_mce(ec, xec))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) goto wrong_mc1_mce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) wrong_mc1_mce:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) pr_emerg(HW_ERR "Corrupted MC1 MCE info?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static bool k8_mc2_mce(u16 ec, u8 xec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) bool ret = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (xec == 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) pr_cont(" in the write data buffers.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) else if (xec == 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) pr_cont(" in the victim data buffers.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) else if (xec == 0x2 && MEM_ERROR(ec))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) pr_cont(": %s error in the L2 cache tags.\n", R4_MSG(ec));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) else if (xec == 0x0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (TLB_ERROR(ec))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) pr_cont("%s error in a Page Descriptor Cache or Guest TLB.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) TT_MSG(ec));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) else if (BUS_ERROR(ec))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) pr_cont(": %s/ECC error in data read from NB: %s.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) R4_MSG(ec), PP_MSG(ec));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) else if (MEM_ERROR(ec)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) u8 r4 = R4(ec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (r4 >= 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) pr_cont(": %s error during data copyback.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) R4_MSG(ec));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) else if (r4 <= 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) pr_cont(": %s parity/ECC error during data "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) "access from L2.\n", R4_MSG(ec));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) ret = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) ret = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) ret = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static bool f15h_mc2_mce(u16 ec, u8 xec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) bool ret = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (TLB_ERROR(ec)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (xec == 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) pr_cont("Data parity TLB read error.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) else if (xec == 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) pr_cont("Poison data provided for TLB fill.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) ret = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) } else if (BUS_ERROR(ec)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (xec > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) ret = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) pr_cont("Error during attempted NB data read.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) } else if (MEM_ERROR(ec)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) switch (xec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) case 0x4 ... 0xc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) pr_cont("%s.\n", f15h_mc2_mce_desc[xec - 0x4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) case 0x10 ... 0x14:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) pr_cont("%s.\n", f15h_mc2_mce_desc[xec - 0x7]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) ret = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) } else if (INT_ERROR(ec)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (xec <= 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) pr_cont("Hardware Assert.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) ret = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static bool f16h_mc2_mce(u16 ec, u8 xec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) u8 r4 = R4(ec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (!MEM_ERROR(ec))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) switch (xec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) case 0x04 ... 0x05:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) pr_cont("%cBUFF parity error.\n", (r4 == R4_RD) ? 'I' : 'O');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) case 0x09 ... 0x0b:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) case 0x0d ... 0x0f:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) pr_cont("ECC error in L2 tag (%s).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) ((r4 == R4_GEN) ? "BankReq" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) ((r4 == R4_SNOOP) ? "Prb" : "Fill")));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) case 0x10 ... 0x19:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) case 0x1b:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) pr_cont("ECC error in L2 data array (%s).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) (((r4 == R4_RD) && !(xec & 0x3)) ? "Hit" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) ((r4 == R4_GEN) ? "Attr" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) ((r4 == R4_EVICT) ? "Vict" : "Fill"))));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) case 0x1c ... 0x1d:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) case 0x1f:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) pr_cont("Parity error in L2 attribute bits (%s).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) ((r4 == R4_RD) ? "Hit" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) ((r4 == R4_GEN) ? "Attr" : "Fill")));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static void decode_mc2_mce(struct mce *m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) u16 ec = EC(m->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) u8 xec = XEC(m->status, xec_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) pr_emerg(HW_ERR "MC2 Error: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) if (!fam_ops.mc2_mce(ec, xec))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) pr_cont(HW_ERR "Corrupted MC2 MCE info?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) static void decode_mc3_mce(struct mce *m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) u16 ec = EC(m->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) u8 xec = XEC(m->status, xec_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) if (boot_cpu_data.x86 >= 0x14) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) pr_emerg("You shouldn't be seeing MC3 MCE on this cpu family,"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) " please report on LKML.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) pr_emerg(HW_ERR "MC3 Error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) if (xec == 0x0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) u8 r4 = R4(ec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (!BUS_ERROR(ec) || (r4 != R4_DRD && r4 != R4_DWR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) goto wrong_mc3_mce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) pr_cont(" during %s.\n", R4_MSG(ec));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) goto wrong_mc3_mce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) wrong_mc3_mce:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) pr_emerg(HW_ERR "Corrupted MC3 MCE info?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) static void decode_mc4_mce(struct mce *m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) unsigned int fam = x86_family(m->cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) int node_id = amd_get_nb_id(m->extcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) u16 ec = EC(m->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) u8 xec = XEC(m->status, 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) u8 offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) pr_emerg(HW_ERR "MC4 Error (node %d): ", node_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) switch (xec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) case 0x0 ... 0xe:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) /* special handling for DRAM ECCs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if (xec == 0x0 || xec == 0x8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) /* no ECCs on F11h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (fam == 0x11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) goto wrong_mc4_mce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) pr_cont("%s.\n", mc4_mce_desc[xec]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (decode_dram_ecc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) decode_dram_ecc(node_id, m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) case 0xf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (TLB_ERROR(ec))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) pr_cont("GART Table Walk data error.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) else if (BUS_ERROR(ec))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) pr_cont("DMA Exclusion Vector Table Walk error.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) goto wrong_mc4_mce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) case 0x19:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (fam == 0x15 || fam == 0x16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) pr_cont("Compute Unit Data Error.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) goto wrong_mc4_mce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) case 0x1c ... 0x1f:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) offset = 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) goto wrong_mc4_mce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) pr_cont("%s.\n", mc4_mce_desc[xec - offset]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) wrong_mc4_mce:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) pr_emerg(HW_ERR "Corrupted MC4 MCE info?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) static void decode_mc5_mce(struct mce *m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) unsigned int fam = x86_family(m->cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) u16 ec = EC(m->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) u8 xec = XEC(m->status, xec_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if (fam == 0xf || fam == 0x11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) goto wrong_mc5_mce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) pr_emerg(HW_ERR "MC5 Error: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) if (INT_ERROR(ec)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (xec <= 0x1f) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) pr_cont("Hardware Assert.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) goto wrong_mc5_mce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) if (xec == 0x0 || xec == 0xc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) pr_cont("%s.\n", mc5_mce_desc[xec]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) else if (xec <= 0xd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) pr_cont("%s parity error.\n", mc5_mce_desc[xec]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) goto wrong_mc5_mce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) wrong_mc5_mce:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) pr_emerg(HW_ERR "Corrupted MC5 MCE info?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) static void decode_mc6_mce(struct mce *m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) u8 xec = XEC(m->status, xec_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) pr_emerg(HW_ERR "MC6 Error: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (xec > 0x5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) goto wrong_mc6_mce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) pr_cont("%s parity error.\n", mc6_mce_desc[xec]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) wrong_mc6_mce:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) pr_emerg(HW_ERR "Corrupted MC6 MCE info?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /* Decode errors according to Scalable MCA specification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) static void decode_smca_error(struct mce *m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) struct smca_hwid *hwid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) enum smca_bank_types bank_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) const char *ip_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) u8 xec = XEC(m->status, xec_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) if (m->bank >= ARRAY_SIZE(smca_banks))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) hwid = smca_banks[m->bank].hwid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if (!hwid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) bank_type = hwid->bank_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (bank_type == SMCA_RESERVED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) pr_emerg(HW_ERR "Bank %d is reserved.\n", m->bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) ip_name = smca_get_long_name(bank_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) pr_emerg(HW_ERR "%s Ext. Error Code: %d", ip_name, xec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) /* Only print the decode of valid error codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) if (xec < smca_mce_descs[bank_type].num_descs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) pr_cont(", %s.\n", smca_mce_descs[bank_type].descs[xec]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) if (bank_type == SMCA_UMC && xec == 0 && decode_dram_ecc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) decode_dram_ecc(topology_die_id(m->extcpu), m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) static inline void amd_decode_err_code(u16 ec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) if (INT_ERROR(ec)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) pr_emerg(HW_ERR "internal: %s\n", UU_MSG(ec));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) pr_emerg(HW_ERR "cache level: %s", LL_MSG(ec));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) if (BUS_ERROR(ec))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) pr_cont(", mem/io: %s", II_MSG(ec));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) pr_cont(", tx: %s", TT_MSG(ec));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (MEM_ERROR(ec) || BUS_ERROR(ec)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) pr_cont(", mem-tx: %s", R4_MSG(ec));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) if (BUS_ERROR(ec))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) pr_cont(", part-proc: %s (%s)", PP_MSG(ec), TO_MSG(ec));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) pr_cont("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) static const char *decode_error_status(struct mce *m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) if (m->status & MCI_STATUS_UC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) if (m->status & MCI_STATUS_PCC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) return "System Fatal error.";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (m->mcgstatus & MCG_STATUS_RIPV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) return "Uncorrected, software restartable error.";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) return "Uncorrected, software containable error.";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) if (m->status & MCI_STATUS_DEFERRED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) return "Deferred error, no action required.";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) return "Corrected error, no action required.";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) struct mce *m = (struct mce *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) unsigned int fam = x86_family(m->cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) int ecc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) if (m->kflags & MCE_HANDLED_CEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) pr_emerg(HW_ERR "%s\n", decode_error_status(m));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) pr_emerg(HW_ERR "CPU:%d (%x:%x:%x) MC%d_STATUS[%s|%s|%s|%s|%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) m->extcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) fam, x86_model(m->cpuid), x86_stepping(m->cpuid),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) m->bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) ((m->status & MCI_STATUS_OVER) ? "Over" : "-"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) ((m->status & MCI_STATUS_UC) ? "UE" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) (m->status & MCI_STATUS_DEFERRED) ? "-" : "CE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) ((m->status & MCI_STATUS_MISCV) ? "MiscV" : "-"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) ((m->status & MCI_STATUS_ADDRV) ? "AddrV" : "-"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) ((m->status & MCI_STATUS_PCC) ? "PCC" : "-"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) if (boot_cpu_has(X86_FEATURE_SMCA)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) u32 low, high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) u32 addr = MSR_AMD64_SMCA_MCx_CONFIG(m->bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) if (!rdmsr_safe(addr, &low, &high) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) (low & MCI_CONFIG_MCAX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) pr_cont("|%s", ((m->status & MCI_STATUS_TCC) ? "TCC" : "-"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) pr_cont("|%s", ((m->status & MCI_STATUS_SYNDV) ? "SyndV" : "-"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) /* do the two bits[14:13] together */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) ecc = (m->status >> 45) & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if (ecc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) pr_cont("|%sECC", ((ecc == 2) ? "C" : "U"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) if (fam >= 0x15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) pr_cont("|%s", (m->status & MCI_STATUS_DEFERRED ? "Deferred" : "-"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) /* F15h, bank4, bit 43 is part of McaStatSubCache. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) if (fam != 0x15 || m->bank != 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) pr_cont("|%s", (m->status & MCI_STATUS_POISON ? "Poison" : "-"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) if (fam >= 0x17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) pr_cont("|%s", (m->status & MCI_STATUS_SCRUB ? "Scrub" : "-"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) pr_cont("]: 0x%016llx\n", m->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) if (m->status & MCI_STATUS_ADDRV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) pr_emerg(HW_ERR "Error Addr: 0x%016llx\n", m->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (m->ppin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) pr_emerg(HW_ERR "PPIN: 0x%016llx\n", m->ppin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) if (boot_cpu_has(X86_FEATURE_SMCA)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) pr_emerg(HW_ERR "IPID: 0x%016llx", m->ipid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) if (m->status & MCI_STATUS_SYNDV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) pr_cont(", Syndrome: 0x%016llx", m->synd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) pr_cont("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) decode_smca_error(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) goto err_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) if (m->tsc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) pr_emerg(HW_ERR "TSC: %llu\n", m->tsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) /* Doesn't matter which member to test. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) if (!fam_ops.mc0_mce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) goto err_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) switch (m->bank) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) decode_mc0_mce(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) decode_mc1_mce(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) decode_mc2_mce(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) decode_mc3_mce(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) decode_mc4_mce(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) decode_mc5_mce(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) decode_mc6_mce(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) err_code:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) amd_decode_err_code(m->status & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) m->kflags |= MCE_HANDLED_EDAC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) static struct notifier_block amd_mce_dec_nb = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) .notifier_call = amd_decode_mce,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) .priority = MCE_PRIO_EDAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) static int __init mce_amd_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) struct cpuinfo_x86 *c = &boot_cpu_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) if (c->x86_vendor != X86_VENDOR_AMD &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) c->x86_vendor != X86_VENDOR_HYGON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) if (cpu_feature_enabled(X86_FEATURE_HYPERVISOR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) if (boot_cpu_has(X86_FEATURE_SMCA)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) xec_mask = 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) switch (c->x86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) case 0xf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) fam_ops.mc0_mce = k8_mc0_mce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) fam_ops.mc1_mce = k8_mc1_mce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) fam_ops.mc2_mce = k8_mc2_mce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) case 0x10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) fam_ops.mc0_mce = f10h_mc0_mce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) fam_ops.mc1_mce = k8_mc1_mce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) fam_ops.mc2_mce = k8_mc2_mce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) case 0x11:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) fam_ops.mc0_mce = k8_mc0_mce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) fam_ops.mc1_mce = k8_mc1_mce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) fam_ops.mc2_mce = k8_mc2_mce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) case 0x12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) fam_ops.mc0_mce = f12h_mc0_mce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) fam_ops.mc1_mce = k8_mc1_mce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) fam_ops.mc2_mce = k8_mc2_mce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) case 0x14:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) fam_ops.mc0_mce = cat_mc0_mce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) fam_ops.mc1_mce = cat_mc1_mce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) fam_ops.mc2_mce = k8_mc2_mce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) case 0x15:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) xec_mask = c->x86_model == 0x60 ? 0x3f : 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) fam_ops.mc0_mce = f15h_mc0_mce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) fam_ops.mc1_mce = f15h_mc1_mce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) fam_ops.mc2_mce = f15h_mc2_mce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) case 0x16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) xec_mask = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) fam_ops.mc0_mce = cat_mc0_mce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) fam_ops.mc1_mce = cat_mc1_mce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) fam_ops.mc2_mce = f16h_mc2_mce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) case 0x17:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) case 0x18:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) pr_warn_once("Decoding supported only on Scalable MCA processors.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) printk(KERN_WARNING "Huh? What family is it: 0x%x?!\n", c->x86);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) pr_info("MCE: In-kernel MCE decoding enabled.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) mce_register_decode_chain(&amd_mce_dec_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) early_initcall(mce_amd_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) #ifdef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) static void __exit mce_amd_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) mce_unregister_decode_chain(&amd_mce_dec_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) MODULE_DESCRIPTION("AMD MCE decoder");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) MODULE_ALIAS("edac-mce-amd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) module_exit(mce_amd_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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