Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  * Freescale Memory Controller kernel module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Author: York Sun <york.sun@nxp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Copyright 2016 NXP Semiconductor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Derived from mpc85xx_edac.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * Author: Dave Jiang <djiang@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  * the terms of the GNU General Public License version 2. This program
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  * is licensed "as is" without any warranty of any kind, whether express
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "edac_module.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "fsl_ddr_edac.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static const struct of_device_id fsl_ddr_mc_err_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	{ .compatible = "fsl,qoriq-memory-controller", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) MODULE_DEVICE_TABLE(of, fsl_ddr_mc_err_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static struct platform_driver fsl_ddr_mc_err_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	.probe = fsl_mc_err_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	.remove = fsl_mc_err_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		.name = "fsl_ddr_mc_err",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		.of_match_table = fsl_ddr_mc_err_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static int __init fsl_ddr_mc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	/* make sure error reporting method is sane */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	switch (edac_op_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	case EDAC_OPSTATE_POLL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	case EDAC_OPSTATE_INT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		edac_op_state = EDAC_OPSTATE_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	res = platform_driver_register(&fsl_ddr_mc_err_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	if (res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		pr_err("MC fails to register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) module_init(fsl_ddr_mc_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static void __exit fsl_ddr_mc_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	platform_driver_unregister(&fsl_ddr_mc_err_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) module_exit(fsl_ddr_mc_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) MODULE_AUTHOR("NXP Semiconductor");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) module_param(edac_op_state, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) MODULE_PARM_DESC(edac_op_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 		 "EDAC Error Reporting state: 0=Poll, 2=Interrupt");