^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Intel E3-1200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2014 Jason Baron <jbaron@akamai.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Support for the E3-1200 processor family. Heavily based on previous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Intel EDAC drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Since the DRAM controller is on the cpu chip, we can use its PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * id to identify these processors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * PCI DRAM controller device ids (Taken from The PCI ID Repository - https://pci-ids.ucw.cz/)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * 0108: Xeon E3-1200 Processor Family DRAM Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * 010c: Xeon E3-1200/2nd Generation Core Processor Family DRAM Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * 0150: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * 0158: Xeon E3-1200 v2/Ivy Bridge DRAM Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * 015c: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * 0c04: Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * 0c08: Xeon E3-1200 v3 Processor DRAM Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * 1918: Xeon E3-1200 v5 Skylake Host Bridge/DRAM Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * 5918: Xeon E3-1200 Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * 3e..: 8th/9th Gen Core Processor Host Bridge/DRAM Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Based on Intel specification:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v3-vol-2-datasheet.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200-family-vol-2-datasheet.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-h-processor-lines-datasheet-vol-2.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * https://www.intel.com/content/www/us/en/products/docs/processors/core/8th-gen-core-family-datasheet-vol-2.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * According to the above datasheet (p.16):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * 6. Software must not access B0/D0/F0 32-bit memory-mapped registers with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * requests that cross a DW boundary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * Thus, we make use of the explicit: lo_hi_readq(), which breaks the readq into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * 2 readl() calls. This restriction may be lifted in subsequent chip releases,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * but lo_hi_readq() ensures that we are safe across all e3-1200 processors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/pci_ids.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/edac.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <linux/io-64-nonatomic-lo-hi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include "edac_module.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define EDAC_MOD_STR "ie31200_edac"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ie31200_printk(level, fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) edac_printk(level, "ie31200", fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PCI_DEVICE_ID_INTEL_IE31200_HB_1 0x0108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PCI_DEVICE_ID_INTEL_IE31200_HB_2 0x010c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PCI_DEVICE_ID_INTEL_IE31200_HB_3 0x0150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PCI_DEVICE_ID_INTEL_IE31200_HB_4 0x0158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PCI_DEVICE_ID_INTEL_IE31200_HB_5 0x015c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PCI_DEVICE_ID_INTEL_IE31200_HB_6 0x0c04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PCI_DEVICE_ID_INTEL_IE31200_HB_7 0x0c08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PCI_DEVICE_ID_INTEL_IE31200_HB_8 0x1918
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PCI_DEVICE_ID_INTEL_IE31200_HB_9 0x5918
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* Coffee Lake-S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK 0x3e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_1 0x3e0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_2 0x3e18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_3 0x3e1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_4 0x3e30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_5 0x3e31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_6 0x3e32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_7 0x3e33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_8 0x3ec2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_9 0x3ec6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_10 0x3eca
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Test if HB is for Skylake or later. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DEVICE_ID_SKYLAKE_OR_LATER(did) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) (((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_8) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_9) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) (((did) & PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK) == \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define IE31200_DIMMS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define IE31200_RANKS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define IE31200_RANKS_PER_CHANNEL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define IE31200_DIMMS_PER_CHANNEL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define IE31200_CHANNELS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Intel IE31200 register addresses - device 0 function 0 - DRAM Controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define IE31200_MCHBAR_LOW 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define IE31200_MCHBAR_HIGH 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define IE31200_MCHBAR_MASK GENMASK_ULL(38, 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define IE31200_MMR_WINDOW_SIZE BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * Error Status Register (16b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * 15 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * 14 Isochronous TBWRR Run Behind FIFO Full
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * (ITCV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * 13 Isochronous TBWRR Run Behind FIFO Put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * (ITSTV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * 12 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * 11 MCH Thermal Sensor Event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * for SMI/SCI/SERR (GTSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * 10 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * 9 LOCK to non-DRAM Memory Flag (LCKF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * 8 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * 7 DRAM Throttle Flag (DTF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * 6:2 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * 1 Multi-bit DRAM ECC Error Flag (DMERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * 0 Single-bit DRAM ECC Error Flag (DSERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define IE31200_ERRSTS 0xc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define IE31200_ERRSTS_UE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define IE31200_ERRSTS_CE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define IE31200_ERRSTS_BITS (IE31200_ERRSTS_UE | IE31200_ERRSTS_CE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * Channel 0 ECC Error Log (64b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * 63:48 Error Column Address (ERRCOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * 47:32 Error Row Address (ERRROW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * 31:29 Error Bank Address (ERRBANK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * 28:27 Error Rank Address (ERRRANK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * 26:24 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * 23:16 Error Syndrome (ERRSYND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * 15: 2 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * 1 Multiple Bit Error Status (MERRSTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * 0 Correctable Error Status (CERRSTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define IE31200_C0ECCERRLOG 0x40c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define IE31200_C1ECCERRLOG 0x44c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define IE31200_C0ECCERRLOG_SKL 0x4048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define IE31200_C1ECCERRLOG_SKL 0x4448
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define IE31200_ECCERRLOG_CE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define IE31200_ECCERRLOG_UE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define IE31200_ECCERRLOG_RANK_BITS GENMASK_ULL(28, 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define IE31200_ECCERRLOG_RANK_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define IE31200_ECCERRLOG_SYNDROME_BITS GENMASK_ULL(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define IE31200_ECCERRLOG_SYNDROME_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define IE31200_ECCERRLOG_SYNDROME(log) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ((log & IE31200_ECCERRLOG_SYNDROME_BITS) >> \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) IE31200_ECCERRLOG_SYNDROME_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define IE31200_CAPID0 0xe4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define IE31200_CAPID0_PDCD BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define IE31200_CAPID0_DDPCD BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define IE31200_CAPID0_ECC BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define IE31200_MAD_DIMM_0_OFFSET 0x5004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define IE31200_MAD_DIMM_0_OFFSET_SKL 0x500C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define IE31200_MAD_DIMM_SIZE GENMASK_ULL(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define IE31200_MAD_DIMM_A_RANK BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define IE31200_MAD_DIMM_A_RANK_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define IE31200_MAD_DIMM_A_RANK_SKL BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define IE31200_MAD_DIMM_A_RANK_SKL_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define IE31200_MAD_DIMM_A_WIDTH BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define IE31200_MAD_DIMM_A_WIDTH_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define IE31200_MAD_DIMM_A_WIDTH_SKL GENMASK_ULL(9, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define IE31200_MAD_DIMM_A_WIDTH_SKL_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* Skylake reports 1GB increments, everything else is 256MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define IE31200_PAGES(n, skl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) (n << (28 + (2 * skl) - PAGE_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int nr_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static struct pci_dev *mci_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static int ie31200_registered = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct ie31200_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) void __iomem *window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) void __iomem *c0errlog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) void __iomem *c1errlog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) enum ie31200_chips {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) IE31200 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct ie31200_dev_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) const char *ctl_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct ie31200_error_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u16 errsts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u16 errsts2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u64 eccerrlog[IE31200_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static const struct ie31200_dev_info ie31200_devs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) [IE31200] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .ctl_name = "IE31200"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct dimm_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u8 size; /* in multiples of 256MB, except Skylake is 1GB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u8 dual_rank : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) x16_width : 2; /* 0 means x8 width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int how_many_channels(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int n_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) unsigned char capid0_2b; /* 2nd byte of CAPID0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) pci_read_config_byte(pdev, IE31200_CAPID0 + 1, &capid0_2b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* check PDCD: Dual Channel Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (capid0_2b & IE31200_CAPID0_PDCD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) edac_dbg(0, "In single channel mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) n_channels = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) edac_dbg(0, "In dual channel mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) n_channels = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* check DDPCD - check if both channels are filled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (capid0_2b & IE31200_CAPID0_DDPCD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) edac_dbg(0, "2 DIMMS per channel disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) edac_dbg(0, "2 DIMMS per channel enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return n_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static bool ecc_capable(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) unsigned char capid0_4b; /* 4th byte of CAPID0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) pci_read_config_byte(pdev, IE31200_CAPID0 + 3, &capid0_4b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (capid0_4b & IE31200_CAPID0_ECC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static int eccerrlog_row(u64 log)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return ((log & IE31200_ECCERRLOG_RANK_BITS) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) IE31200_ECCERRLOG_RANK_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static void ie31200_clear_error_info(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * Clear any error bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * (Yes, we really clear bits by writing 1 to them.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) pci_write_bits16(to_pci_dev(mci->pdev), IE31200_ERRSTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) IE31200_ERRSTS_BITS, IE31200_ERRSTS_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static void ie31200_get_and_clear_error_info(struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct ie31200_error_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct ie31200_priv *priv = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) pdev = to_pci_dev(mci->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * This is a mess because there is no atomic way to read all the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * registers at once and the registers can transition from CE being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * overwritten by UE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) pci_read_config_word(pdev, IE31200_ERRSTS, &info->errsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (!(info->errsts & IE31200_ERRSTS_BITS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) info->eccerrlog[0] = lo_hi_readq(priv->c0errlog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (nr_channels == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) info->eccerrlog[1] = lo_hi_readq(priv->c1errlog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) pci_read_config_word(pdev, IE31200_ERRSTS, &info->errsts2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * If the error is the same for both reads then the first set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * of reads is valid. If there is a change then there is a CE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * with no info and the second set of reads is valid and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * should be UE info.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) info->eccerrlog[0] = lo_hi_readq(priv->c0errlog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (nr_channels == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) info->eccerrlog[1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) lo_hi_readq(priv->c1errlog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) ie31200_clear_error_info(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static void ie31200_process_error_info(struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct ie31200_error_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) int channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u64 log;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (!(info->errsts & IE31200_ERRSTS_BITS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) -1, -1, -1, "UE overwrote CE", "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) info->errsts = info->errsts2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) for (channel = 0; channel < nr_channels; channel++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) log = info->eccerrlog[channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (log & IE31200_ECCERRLOG_UE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) eccerrlog_row(log),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) channel, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) "ie31200 UE", "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) } else if (log & IE31200_ECCERRLOG_CE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) IE31200_ECCERRLOG_SYNDROME(log),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) eccerrlog_row(log),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) channel, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) "ie31200 CE", "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static void ie31200_check(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct ie31200_error_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) edac_dbg(1, "MC%d\n", mci->mc_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ie31200_get_and_clear_error_info(mci, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ie31200_process_error_info(mci, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static void __iomem *ie31200_map_mchbar(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u64 mchbar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u32 mchbar_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u32 mchbar_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) void __iomem *window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) pci_read_config_dword(pdev, IE31200_MCHBAR_LOW, &u.mchbar_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) pci_read_config_dword(pdev, IE31200_MCHBAR_HIGH, &u.mchbar_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u.mchbar &= IE31200_MCHBAR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (u.mchbar != (resource_size_t)u.mchbar) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) ie31200_printk(KERN_ERR, "mmio space beyond accessible range (0x%llx)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) (unsigned long long)u.mchbar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) window = ioremap(u.mchbar, IE31200_MMR_WINDOW_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (!window)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) ie31200_printk(KERN_ERR, "Cannot map mmio space at 0x%llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) (unsigned long long)u.mchbar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static void __skl_populate_dimm_info(struct dimm_data *dd, u32 addr_decode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) int chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) dd->size = (addr_decode >> (chan << 4)) & IE31200_MAD_DIMM_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) dd->dual_rank = (addr_decode & (IE31200_MAD_DIMM_A_RANK_SKL << (chan << 4))) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) dd->x16_width = ((addr_decode & (IE31200_MAD_DIMM_A_WIDTH_SKL << (chan << 4))) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) (IE31200_MAD_DIMM_A_WIDTH_SKL_SHIFT + (chan << 4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static void __populate_dimm_info(struct dimm_data *dd, u32 addr_decode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) int chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) dd->size = (addr_decode >> (chan << 3)) & IE31200_MAD_DIMM_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) dd->dual_rank = (addr_decode & (IE31200_MAD_DIMM_A_RANK << chan)) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) dd->x16_width = (addr_decode & (IE31200_MAD_DIMM_A_WIDTH << chan)) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static void populate_dimm_info(struct dimm_data *dd, u32 addr_decode, int chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) bool skl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (skl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) __skl_populate_dimm_info(dd, addr_decode, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) __populate_dimm_info(dd, addr_decode, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static int ie31200_probe1(struct pci_dev *pdev, int dev_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) int i, j, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct mem_ctl_info *mci = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct edac_mc_layer layers[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct dimm_data dimm_info[IE31200_CHANNELS][IE31200_DIMMS_PER_CHANNEL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) void __iomem *window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct ie31200_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) u32 addr_decode, mad_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * Kaby Lake, Coffee Lake seem to work like Skylake. Please re-visit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * this logic when adding new CPU support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) bool skl = DEVICE_ID_SKYLAKE_OR_LATER(pdev->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) edac_dbg(0, "MC:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (!ecc_capable(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ie31200_printk(KERN_INFO, "No ECC support\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) nr_channels = how_many_channels(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) layers[0].size = IE31200_DIMMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) layers[0].is_virt_csrow = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) layers[1].type = EDAC_MC_LAYER_CHANNEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) layers[1].size = nr_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) layers[1].is_virt_csrow = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) sizeof(struct ie31200_priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (!mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) window = ie31200_map_mchbar(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (!window) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) goto fail_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) edac_dbg(3, "MC: init mci\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) mci->pdev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (skl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) mci->mtype_cap = MEM_FLAG_DDR4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) mci->mtype_cap = MEM_FLAG_DDR3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) mci->edac_ctl_cap = EDAC_FLAG_SECDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) mci->edac_cap = EDAC_FLAG_SECDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) mci->mod_name = EDAC_MOD_STR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) mci->ctl_name = ie31200_devs[dev_idx].ctl_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) mci->dev_name = pci_name(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) mci->edac_check = ie31200_check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) mci->ctl_page_to_phys = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) priv = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) priv->window = window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (skl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) priv->c0errlog = window + IE31200_C0ECCERRLOG_SKL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) priv->c1errlog = window + IE31200_C1ECCERRLOG_SKL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) mad_offset = IE31200_MAD_DIMM_0_OFFSET_SKL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) priv->c0errlog = window + IE31200_C0ECCERRLOG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) priv->c1errlog = window + IE31200_C1ECCERRLOG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) mad_offset = IE31200_MAD_DIMM_0_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* populate DIMM info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) for (i = 0; i < IE31200_CHANNELS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) addr_decode = readl(window + mad_offset +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) (i * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) edac_dbg(0, "addr_decode: 0x%x\n", addr_decode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) for (j = 0; j < IE31200_DIMMS_PER_CHANNEL; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) populate_dimm_info(&dimm_info[i][j], addr_decode, j,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) edac_dbg(0, "size: 0x%x, rank: %d, width: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) dimm_info[i][j].size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) dimm_info[i][j].dual_rank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) dimm_info[i][j].x16_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * The dram rank boundary (DRB) reg values are boundary addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * for each DRAM rank with a granularity of 64MB. DRB regs are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * cumulative; the last one will contain the total memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * contained in all ranks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) for (i = 0; i < IE31200_DIMMS_PER_CHANNEL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) for (j = 0; j < IE31200_CHANNELS; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct dimm_info *dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) unsigned long nr_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) nr_pages = IE31200_PAGES(dimm_info[j][i].size, skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (nr_pages == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (dimm_info[j][i].dual_rank) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) nr_pages = nr_pages / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) dimm = edac_get_dimm(mci, (i * 2) + 1, j, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) dimm->nr_pages = nr_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) dimm->grain = 8; /* just a guess */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (skl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) dimm->mtype = MEM_DDR4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) dimm->mtype = MEM_DDR3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) dimm->dtype = DEV_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) dimm->edac_mode = EDAC_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) dimm = edac_get_dimm(mci, i * 2, j, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) dimm->nr_pages = nr_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) dimm->grain = 8; /* same guess */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (skl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) dimm->mtype = MEM_DDR4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) dimm->mtype = MEM_DDR3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) dimm->dtype = DEV_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) dimm->edac_mode = EDAC_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) ie31200_clear_error_info(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (edac_mc_add_mc(mci)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) edac_dbg(3, "MC: failed edac_mc_add_mc()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) goto fail_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* get this far and it's successful */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) edac_dbg(3, "MC: success\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) fail_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) iounmap(window);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) fail_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static int ie31200_init_one(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) edac_dbg(0, "MC:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (pci_enable_device(pdev) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) rc = ie31200_probe1(pdev, ent->driver_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (rc == 0 && !mci_pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) mci_pdev = pci_dev_get(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static void ie31200_remove_one(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct mem_ctl_info *mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct ie31200_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) edac_dbg(0, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) pci_dev_put(mci_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) mci_pdev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) mci = edac_mc_del_mc(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (!mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) priv = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) iounmap(priv->window);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static const struct pci_device_id ie31200_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) { PCI_VEND_DEV(INTEL, IE31200_HB_1), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) { PCI_VEND_DEV(INTEL, IE31200_HB_2), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) { PCI_VEND_DEV(INTEL, IE31200_HB_3), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) { PCI_VEND_DEV(INTEL, IE31200_HB_4), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) { PCI_VEND_DEV(INTEL, IE31200_HB_5), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) { PCI_VEND_DEV(INTEL, IE31200_HB_6), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) { PCI_VEND_DEV(INTEL, IE31200_HB_7), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) { PCI_VEND_DEV(INTEL, IE31200_HB_8), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) { PCI_VEND_DEV(INTEL, IE31200_HB_9), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_1), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_2), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_3), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_4), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_5), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_6), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_7), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_8), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_9), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_10), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) { 0, } /* 0 terminated list. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) MODULE_DEVICE_TABLE(pci, ie31200_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static struct pci_driver ie31200_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .name = EDAC_MOD_STR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .probe = ie31200_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .remove = ie31200_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .id_table = ie31200_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static int __init ie31200_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) int pci_rc, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) edac_dbg(3, "MC:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /* Ensure that the OPSTATE is set correctly for POLL or NMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) opstate_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) pci_rc = pci_register_driver(&ie31200_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (pci_rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) goto fail0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (!mci_pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) ie31200_registered = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) for (i = 0; ie31200_pci_tbl[i].vendor != 0; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) mci_pdev = pci_get_device(ie31200_pci_tbl[i].vendor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) ie31200_pci_tbl[i].device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (mci_pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (!mci_pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) edac_dbg(0, "ie31200 pci_get_device fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) pci_rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) goto fail1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) pci_rc = ie31200_init_one(mci_pdev, &ie31200_pci_tbl[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (pci_rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) edac_dbg(0, "ie31200 init fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) pci_rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) goto fail1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) fail1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) pci_unregister_driver(&ie31200_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) fail0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) pci_dev_put(mci_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return pci_rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static void __exit ie31200_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) edac_dbg(3, "MC:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) pci_unregister_driver(&ie31200_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (!ie31200_registered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) ie31200_remove_one(mci_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) module_init(ie31200_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) module_exit(ie31200_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) MODULE_AUTHOR("Jason Baron <jbaron@akamai.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) MODULE_DESCRIPTION("MC support for Intel Processor E31200 memory hub controllers");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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