^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Intel D82875P Memory Controller kernel module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * (C) 2003 Linux Networx (http://lnxi.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This file may be distributed under the terms of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * GNU General Public License.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Written by Thayne Harbaugh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Contributors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Wang Zhenyu at intel.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * $Id: edac_i82875p.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Note: E7210 appears same as D82875P - zhenyu.z.wang at intel.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pci_ids.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/edac.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "edac_module.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define EDAC_MOD_STR "i82875p_edac"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define i82875p_printk(level, fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) edac_printk(level, "i82875p", fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define i82875p_mc_printk(mci, level, fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) edac_mc_chipset_printk(mci, level, "i82875p", fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #ifndef PCI_DEVICE_ID_INTEL_82875_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PCI_DEVICE_ID_INTEL_82875_0 0x2578
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #endif /* PCI_DEVICE_ID_INTEL_82875_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #ifndef PCI_DEVICE_ID_INTEL_82875_6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PCI_DEVICE_ID_INTEL_82875_6 0x257e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #endif /* PCI_DEVICE_ID_INTEL_82875_6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* four csrows in dual channel, eight in single channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define I82875P_NR_DIMMS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define I82875P_NR_CSROWS(nr_chans) (I82875P_NR_DIMMS / (nr_chans))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Intel 82875p register addresses - device 0 function 0 - DRAM Controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define I82875P_EAP 0x58 /* Error Address Pointer (32b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * 31:12 block address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * 11:0 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define I82875P_DERRSYN 0x5c /* DRAM Error Syndrome (8b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * 7:0 DRAM ECC Syndrome
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define I82875P_DES 0x5d /* DRAM Error Status (8b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * 7:1 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * 0 Error channel 0/1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define I82875P_ERRSTS 0xc8 /* Error Status Register (16b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * 15:10 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * 9 non-DRAM lock error (ndlock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * 8 Sftwr Generated SMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * 7 ECC UE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * 6 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * 5 MCH detects unimplemented cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * 4 AGP access outside GA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * 3 Invalid AGP access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * 2 Invalid GA translation table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * 1 Unsupported AGP command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * 0 ECC CE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define I82875P_ERRCMD 0xca /* Error Command (16b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * 15:10 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * 9 SERR on non-DRAM lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * 8 SERR on ECC UE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * 7 SERR on ECC CE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * 6 target abort on high exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * 5 detect unimplemented cyc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * 4 AGP access outside of GA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * 3 SERR on invalid AGP access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * 2 invalid translation table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * 1 SERR on unsupported AGP command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * 0 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Intel 82875p register addresses - device 6 function 0 - DRAM Controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define I82875P_PCICMD6 0x04 /* PCI Command Register (16b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * 15:10 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * 9 fast back-to-back - ro 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * 8 SERR enable - ro 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * 7 addr/data stepping - ro 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * 6 parity err enable - ro 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * 5 VGA palette snoop - ro 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * 4 mem wr & invalidate - ro 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * 3 special cycle - ro 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * 2 bus master - ro 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * 1 mem access dev6 - 0(dis),1(en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * 0 IO access dev3 - 0(dis),1(en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define I82875P_BAR6 0x10 /* Mem Delays Base ADDR Reg (32b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * 31:12 mem base addr [31:12]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * 11:4 address mask - ro 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * 3 prefetchable - ro 0(non),1(pre)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * 2:1 mem type - ro 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * 0 mem space - ro 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Intel 82875p MMIO register space - device 0 function 0 - MMR space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define I82875P_DRB_SHIFT 26 /* 64MiB grain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define I82875P_DRB 0x00 /* DRAM Row Boundary (8b x 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * 7 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * 6:0 64MiB row boundary addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define I82875P_DRA 0x10 /* DRAM Row Attribute (4b x 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * 7 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * 6:4 row attr row 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * 3 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * 2:0 row attr row 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * 000 = 4KiB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * 001 = 8KiB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * 010 = 16KiB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * 011 = 32KiB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define I82875P_DRC 0x68 /* DRAM Controller Mode (32b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * 31:30 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * 29 init complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * 28:23 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * 22:21 nr chan 00=1,01=2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * 20 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * 19:18 Data Integ Mode 00=none,01=ecc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * 17:11 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * 10:8 refresh mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * 7 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * 6:4 mode select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * 3:2 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * 1:0 DRAM type 01=DDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) enum i82875p_chips {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) I82875P = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct i82875p_pvt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct pci_dev *ovrfl_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) void __iomem *ovrfl_window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct i82875p_dev_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) const char *ctl_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct i82875p_error_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u16 errsts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u32 eap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u8 des;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u8 derrsyn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u16 errsts2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static const struct i82875p_dev_info i82875p_devs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) [I82875P] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .ctl_name = "i82875p"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static struct pci_dev *mci_pdev; /* init dev: in case that AGP code has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * already registered driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static struct edac_pci_ctl_info *i82875p_pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static void i82875p_get_error_info(struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct i82875p_error_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) pdev = to_pci_dev(mci->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * This is a mess because there is no atomic way to read all the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * registers at once and the registers can transition from CE being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * overwritten by UE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) pci_read_config_word(pdev, I82875P_ERRSTS, &info->errsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (!(info->errsts & 0x0081))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) pci_read_config_dword(pdev, I82875P_EAP, &info->eap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) pci_read_config_byte(pdev, I82875P_DES, &info->des);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) pci_read_config_byte(pdev, I82875P_DERRSYN, &info->derrsyn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) pci_read_config_word(pdev, I82875P_ERRSTS, &info->errsts2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * If the error is the same then we can for both reads then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * the first set of reads is valid. If there is a change then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * there is a CE no info and the second set of reads is valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * and should be UE info.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if ((info->errsts ^ info->errsts2) & 0x0081) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) pci_read_config_dword(pdev, I82875P_EAP, &info->eap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) pci_read_config_byte(pdev, I82875P_DES, &info->des);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) pci_read_config_byte(pdev, I82875P_DERRSYN, &info->derrsyn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) pci_write_bits16(pdev, I82875P_ERRSTS, 0x0081, 0x0081);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static int i82875p_process_error_info(struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct i82875p_error_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int handle_errors)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int row, multi_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) multi_chan = mci->csrows[0]->nr_channels - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (!(info->errsts & 0x0081))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (!handle_errors)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if ((info->errsts ^ info->errsts2) & 0x0081) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) -1, -1, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) "UE overwrote CE", "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) info->errsts = info->errsts2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) info->eap >>= PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) row = edac_mc_find_csrow_by_page(mci, info->eap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (info->errsts & 0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) info->eap, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) row, -1, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) "i82875p UE", "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) info->eap, 0, info->derrsyn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) row, multi_chan ? (info->des & 0x1) : 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) -1, "i82875p CE", "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static void i82875p_check(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct i82875p_error_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) edac_dbg(1, "MC%d\n", mci->mc_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) i82875p_get_error_info(mci, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) i82875p_process_error_info(mci, &info, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* Return 0 on success or 1 on failure. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static int i82875p_setup_overfl_dev(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct pci_dev **ovrfl_pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) void __iomem **ovrfl_window)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) void __iomem *window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) *ovrfl_pdev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) *ovrfl_window = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) dev = pci_get_device(PCI_VEND_DEV(INTEL, 82875_6), NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (dev == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* Intel tells BIOS developers to hide device 6 which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * configures the overflow device access containing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * the DRBs - this is where we expose device 6.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) pci_write_bits8(pdev, 0xf4, 0x2, 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) dev = pci_scan_single_device(pdev->bus, PCI_DEVFN(6, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (dev == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) pci_bus_assign_resources(dev->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) pci_bus_add_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) *ovrfl_pdev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (pci_enable_device(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) i82875p_printk(KERN_ERR, "%s(): Failed to enable overflow "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) "device\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (pci_request_regions(dev, pci_name(dev))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #ifdef CORRECT_BIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) goto fail0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* cache is irrelevant for PCI bus reads/writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) window = pci_ioremap_bar(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (window == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) i82875p_printk(KERN_ERR, "%s(): Failed to ioremap bar6\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) goto fail1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) *ovrfl_window = window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) fail1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) pci_release_regions(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #ifdef CORRECT_BIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) fail0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) pci_disable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* NOTE: the ovrfl proc entry and pci_dev are intentionally left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* Return 1 if dual channel mode is active. Else return 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static inline int dual_channel_active(u32 drc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return (drc >> 21) & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static void i82875p_init_csrows(struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) void __iomem * ovrfl_window, u32 drc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct csrow_info *csrow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct dimm_info *dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) unsigned nr_chans = dual_channel_active(drc) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) unsigned long last_cumul_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) u32 drc_ddim; /* DRAM Data Integrity Mode 0=none,2=edac */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u32 cumul_size, nr_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) int index, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) drc_ddim = (drc >> 18) & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) last_cumul_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* The dram row boundary (DRB) reg values are boundary address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * for each DRAM row with a granularity of 32 or 64MB (single/dual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * channel operation). DRB regs are cumulative; therefore DRB7 will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * contain the total memory contained in all eight rows.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) for (index = 0; index < mci->nr_csrows; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) csrow = mci->csrows[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) value = readb(ovrfl_window + I82875P_DRB + index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) cumul_size = value << (I82875P_DRB_SHIFT - PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) edac_dbg(3, "(%d) cumul_size 0x%x\n", index, cumul_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (cumul_size == last_cumul_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) continue; /* not populated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) csrow->first_page = last_cumul_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) csrow->last_page = cumul_size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) nr_pages = cumul_size - last_cumul_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) last_cumul_size = cumul_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) for (j = 0; j < nr_chans; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) dimm = csrow->channels[j]->dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) dimm->nr_pages = nr_pages / nr_chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) dimm->grain = 1 << 12; /* I82875P_EAP has 4KiB reolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) dimm->mtype = MEM_DDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) dimm->dtype = DEV_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) dimm->edac_mode = drc_ddim ? EDAC_SECDED : EDAC_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static int i82875p_probe1(struct pci_dev *pdev, int dev_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) int rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct mem_ctl_info *mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct edac_mc_layer layers[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct i82875p_pvt *pvt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct pci_dev *ovrfl_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) void __iomem *ovrfl_window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) u32 drc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) u32 nr_chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct i82875p_error_info discard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) edac_dbg(0, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (i82875p_setup_overfl_dev(pdev, &ovrfl_pdev, &ovrfl_window))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) drc = readl(ovrfl_window + I82875P_DRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) nr_chans = dual_channel_active(drc) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) layers[0].size = I82875P_NR_CSROWS(nr_chans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) layers[0].is_virt_csrow = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) layers[1].type = EDAC_MC_LAYER_CHANNEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) layers[1].size = nr_chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) layers[1].is_virt_csrow = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (!mci) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) goto fail0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) edac_dbg(3, "init mci\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) mci->pdev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) mci->mtype_cap = MEM_FLAG_DDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) mci->edac_cap = EDAC_FLAG_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) mci->mod_name = EDAC_MOD_STR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) mci->ctl_name = i82875p_devs[dev_idx].ctl_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) mci->dev_name = pci_name(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) mci->edac_check = i82875p_check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) mci->ctl_page_to_phys = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) edac_dbg(3, "init pvt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) pvt = (struct i82875p_pvt *)mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) pvt->ovrfl_pdev = ovrfl_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) pvt->ovrfl_window = ovrfl_window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) i82875p_init_csrows(mci, pdev, ovrfl_window, drc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) i82875p_get_error_info(mci, &discard); /* clear counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* Here we assume that we will never see multiple instances of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * type of memory controller. The ID is therefore hardcoded to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (edac_mc_add_mc(mci)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) edac_dbg(3, "failed edac_mc_add_mc()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) goto fail1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* allocating generic PCI control info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) i82875p_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (!i82875p_pci) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) "%s(): Unable to create PCI control\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) "%s(): PCI error report via EDAC not setup\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* get this far and it's successful */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) edac_dbg(3, "success\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) fail1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) fail0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) iounmap(ovrfl_window);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) pci_release_regions(ovrfl_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) pci_disable_device(ovrfl_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* NOTE: the ovrfl proc entry and pci_dev are intentionally left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* returns count (>= 0), or negative on error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static int i82875p_init_one(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) edac_dbg(0, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) i82875p_printk(KERN_INFO, "i82875p init one\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (pci_enable_device(pdev) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) rc = i82875p_probe1(pdev, ent->driver_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (mci_pdev == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) mci_pdev = pci_dev_get(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static void i82875p_remove_one(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct mem_ctl_info *mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct i82875p_pvt *pvt = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) edac_dbg(0, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (i82875p_pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) edac_pci_release_generic_ctl(i82875p_pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) pvt = (struct i82875p_pvt *)mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (pvt->ovrfl_window)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) iounmap(pvt->ovrfl_window);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (pvt->ovrfl_pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #ifdef CORRECT_BIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) pci_release_regions(pvt->ovrfl_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #endif /*CORRECT_BIOS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) pci_disable_device(pvt->ovrfl_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) pci_dev_put(pvt->ovrfl_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static const struct pci_device_id i82875p_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) PCI_VEND_DEV(INTEL, 82875_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) I82875P},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) } /* 0 terminated list. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) MODULE_DEVICE_TABLE(pci, i82875p_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static struct pci_driver i82875p_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .name = EDAC_MOD_STR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .probe = i82875p_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .remove = i82875p_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .id_table = i82875p_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static int __init i82875p_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) int pci_rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) edac_dbg(3, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /* Ensure that the OPSTATE is set correctly for POLL or NMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) opstate_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) pci_rc = pci_register_driver(&i82875p_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (pci_rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) goto fail0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (mci_pdev == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) PCI_DEVICE_ID_INTEL_82875_0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (!mci_pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) edac_dbg(0, "875p pci_get_device fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) pci_rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) goto fail1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) pci_rc = i82875p_init_one(mci_pdev, i82875p_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (pci_rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) edac_dbg(0, "875p init fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) pci_rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) goto fail1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) fail1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) pci_unregister_driver(&i82875p_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) fail0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) pci_dev_put(mci_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return pci_rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static void __exit i82875p_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) edac_dbg(3, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) i82875p_remove_one(mci_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) pci_dev_put(mci_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) pci_unregister_driver(&i82875p_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) module_init(i82875p_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) module_exit(i82875p_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) MODULE_DESCRIPTION("MC support for Intel 82875 memory hub controllers");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) module_param(edac_op_state, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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