Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Intel 82860 Memory Controller kernel module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * (C) 2005 Red Hat (http://www.redhat.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * This file may be distributed under the terms of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * GNU General Public License.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Written by Ben Woodard <woodard@redhat.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * shamelessly copied from and based upon the edac_i82875 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * by Thayne Harbaugh of Linux Networx. (http://lnxi.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/pci_ids.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/edac.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include "edac_module.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define EDAC_MOD_STR	"i82860_edac"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define i82860_printk(level, fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	edac_printk(level, "i82860", fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define i82860_mc_printk(mci, level, fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	edac_mc_chipset_printk(mci, level, "i82860", fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #ifndef PCI_DEVICE_ID_INTEL_82860_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define PCI_DEVICE_ID_INTEL_82860_0	0x2531
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #endif				/* PCI_DEVICE_ID_INTEL_82860_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define I82860_MCHCFG 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define I82860_GBA 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define I82860_GBA_MASK 0x7FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define I82860_GBA_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define I82860_ERRSTS 0xC8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define I82860_EAP 0xE4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define I82860_DERRCTL_STS 0xE2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) enum i82860_chips {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	I82860 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) struct i82860_dev_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	const char *ctl_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) struct i82860_error_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	u16 errsts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	u32 eap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	u16 derrsyn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	u16 errsts2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) static const struct i82860_dev_info i82860_devs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	[I82860] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		.ctl_name = "i82860"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static struct pci_dev *mci_pdev;	/* init dev: in case that AGP code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 					 * has already registered driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 					 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) static struct edac_pci_ctl_info *i82860_pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static void i82860_get_error_info(struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 				struct i82860_error_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	pdev = to_pci_dev(mci->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	 * This is a mess because there is no atomic way to read all the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	 * registers at once and the registers can transition from CE being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	 * overwritten by UE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	pci_read_config_word(pdev, I82860_ERRSTS, &info->errsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	pci_read_config_dword(pdev, I82860_EAP, &info->eap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	pci_read_config_word(pdev, I82860_DERRCTL_STS, &info->derrsyn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	pci_read_config_word(pdev, I82860_ERRSTS, &info->errsts2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	pci_write_bits16(pdev, I82860_ERRSTS, 0x0003, 0x0003);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	 * If the error is the same for both reads then the first set of reads
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	 * is valid.  If there is a change then there is a CE no info and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	 * second set of reads is valid and should be UE info.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	if (!(info->errsts2 & 0x0003))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	if ((info->errsts ^ info->errsts2) & 0x0003) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		pci_read_config_dword(pdev, I82860_EAP, &info->eap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		pci_read_config_word(pdev, I82860_DERRCTL_STS, &info->derrsyn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) static int i82860_process_error_info(struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 				struct i82860_error_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 				int handle_errors)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	struct dimm_info *dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	int row;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	if (!(info->errsts2 & 0x0003))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	if (!handle_errors)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	if ((info->errsts ^ info->errsts2) & 0x0003) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 				     -1, -1, -1, "UE overwrote CE", "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		info->errsts = info->errsts2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	info->eap >>= PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	row = edac_mc_find_csrow_by_page(mci, info->eap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	dimm = mci->csrows[row]->channels[0]->dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	if (info->errsts & 0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 				     info->eap, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 				     dimm->location[0], dimm->location[1], -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 				     "i82860 UE", "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 				     info->eap, 0, info->derrsyn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 				     dimm->location[0], dimm->location[1], -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 				     "i82860 CE", "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static void i82860_check(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	struct i82860_error_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	edac_dbg(1, "MC%d\n", mci->mc_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	i82860_get_error_info(mci, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	i82860_process_error_info(mci, &info, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static void i82860_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	unsigned long last_cumul_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	u16 mchcfg_ddim;	/* DRAM Data Integrity Mode 0=none, 2=edac */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	u16 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	u32 cumul_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	struct csrow_info *csrow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	struct dimm_info *dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	pci_read_config_word(pdev, I82860_MCHCFG, &mchcfg_ddim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	mchcfg_ddim = mchcfg_ddim & 0x180;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	last_cumul_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	/* The group row boundary (GRA) reg values are boundary address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	 * for each DRAM row with a granularity of 16MB.  GRA regs are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	 * cumulative; therefore GRA15 will contain the total memory contained
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	 * in all eight rows.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	for (index = 0; index < mci->nr_csrows; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		csrow = mci->csrows[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		dimm = csrow->channels[0]->dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		pci_read_config_word(pdev, I82860_GBA + index * 2, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		cumul_size = (value & I82860_GBA_MASK) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 			(I82860_GBA_SHIFT - PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		edac_dbg(3, "(%d) cumul_size 0x%x\n", index, cumul_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		if (cumul_size == last_cumul_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			continue;	/* not populated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		csrow->first_page = last_cumul_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		csrow->last_page = cumul_size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		dimm->nr_pages = cumul_size - last_cumul_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		last_cumul_size = cumul_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		dimm->grain = 1 << 12;	/* I82860_EAP has 4KiB reolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		dimm->mtype = MEM_RMBS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		dimm->dtype = DEV_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		dimm->edac_mode = mchcfg_ddim ? EDAC_SECDED : EDAC_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int i82860_probe1(struct pci_dev *pdev, int dev_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	struct mem_ctl_info *mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	struct edac_mc_layer layers[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	struct i82860_error_info discard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	 * RDRAM has channels but these don't map onto the csrow abstraction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	 * According with the datasheet, there are 2 Rambus channels, supporting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	 * up to 16 direct RDRAM devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	 * The device groups from the GRA registers seem to map reasonably
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	 * well onto the notion of a chip select row.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	 * There are 16 GRA registers and since the name is associated with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	 * the channel and the GRA registers map to physical devices so we are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	 * going to make 1 channel for group.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	layers[0].type = EDAC_MC_LAYER_CHANNEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	layers[0].size = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	layers[0].is_virt_csrow = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	layers[1].type = EDAC_MC_LAYER_SLOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	layers[1].size = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	layers[1].is_virt_csrow = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	if (!mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	edac_dbg(3, "init mci\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	mci->pdev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	mci->mtype_cap = MEM_FLAG_DDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	/* I"m not sure about this but I think that all RDRAM is SECDED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	mci->edac_cap = EDAC_FLAG_SECDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	mci->mod_name = EDAC_MOD_STR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	mci->ctl_name = i82860_devs[dev_idx].ctl_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	mci->dev_name = pci_name(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	mci->edac_check = i82860_check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	mci->ctl_page_to_phys = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	i82860_init_csrows(mci, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	i82860_get_error_info(mci, &discard);	/* clear counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	/* Here we assume that we will never see multiple instances of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	 * type of memory controller.  The ID is therefore hardcoded to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	if (edac_mc_add_mc(mci)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		edac_dbg(3, "failed edac_mc_add_mc()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	/* allocating generic PCI control info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	i82860_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	if (!i82860_pci) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 			"%s(): Unable to create PCI control\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 			__func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 			"%s(): PCI error report via EDAC not setup\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 			__func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	/* get this far and it's successful */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	edac_dbg(3, "success\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* returns count (>= 0), or negative on error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static int i82860_init_one(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 			   const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	edac_dbg(0, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	i82860_printk(KERN_INFO, "i82860 init one\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	if (pci_enable_device(pdev) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	rc = i82860_probe1(pdev, ent->driver_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	if (rc == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		mci_pdev = pci_dev_get(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static void i82860_remove_one(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	struct mem_ctl_info *mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	edac_dbg(0, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	if (i82860_pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		edac_pci_release_generic_ctl(i82860_pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static const struct pci_device_id i82860_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	 PCI_VEND_DEV(INTEL, 82860_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	 I82860},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	 }			/* 0 terminated list. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) MODULE_DEVICE_TABLE(pci, i82860_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static struct pci_driver i82860_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	.name = EDAC_MOD_STR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	.probe = i82860_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	.remove = i82860_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	.id_table = i82860_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static int __init i82860_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	int pci_rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	edac_dbg(3, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)        /* Ensure that the OPSTATE is set correctly for POLL or NMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)        opstate_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	if ((pci_rc = pci_register_driver(&i82860_driver)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		goto fail0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	if (!mci_pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 					PCI_DEVICE_ID_INTEL_82860_0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		if (mci_pdev == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 			edac_dbg(0, "860 pci_get_device fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 			pci_rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 			goto fail1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		pci_rc = i82860_init_one(mci_pdev, i82860_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		if (pci_rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 			edac_dbg(0, "860 init fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 			pci_rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 			goto fail1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) fail1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	pci_unregister_driver(&i82860_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) fail0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	pci_dev_put(mci_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	return pci_rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static void __exit i82860_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	edac_dbg(3, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	pci_unregister_driver(&i82860_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	pci_dev_put(mci_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) module_init(i82860_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) module_exit(i82860_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com) "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		"Ben Woodard <woodard@redhat.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) MODULE_DESCRIPTION("ECC support for Intel 82860 memory hub controllers");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) module_param(edac_op_state, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");