^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Intel 5400 class Memory Controllers kernel module (Seaburg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This file may be distributed under the terms of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * GNU General Public License.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2008 by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Ben Woodard <woodard@redhat.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Mauro Carvalho Chehab
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Red Hat Inc. https://www.redhat.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Forked and adapted from the i5000_edac driver which was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * written by Douglas Thompson Linux Networx <norsk5@xmission.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * This module is based on the following document:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Intel 5400 Chipset Memory Controller Hub (MCH) - Datasheet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * http://developer.intel.com/design/chipsets/datashts/313070.htm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * This Memory Controller manages DDR2 FB-DIMMs. It has 2 branches, each with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * 2 channels operating in lockstep no-mirror mode. Each channel can have up to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * 4 dimm's, each with up to 8GB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/pci_ids.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/edac.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/mmzone.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include "edac_module.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Alter this version for the I5400 module when modifications are made
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define I5400_REVISION " Ver: 1.0.0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define EDAC_MOD_STR "i5400_edac"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define i5400_printk(level, fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) edac_printk(level, "i5400", fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define i5400_mc_printk(mci, level, fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) edac_mc_chipset_printk(mci, level, "i5400", fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Limits for i5400 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MAX_BRANCHES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CHANNELS_PER_BRANCH 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DIMMS_PER_CHANNEL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MAX_CHANNELS (MAX_BRANCHES * CHANNELS_PER_BRANCH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Device 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * Function 0: System Address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * Function 1: Memory Branch Map, Control, Errors Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * Function 2: FSB Error Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * All 3 functions of Device 16 (0,1,2) share the SAME DID and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * uses PCI_DEVICE_ID_INTEL_5400_ERR for device 16 (0,1,2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * PCI_DEVICE_ID_INTEL_5400_FBD0 and PCI_DEVICE_ID_INTEL_5400_FBD1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * for device 21 (0,1).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* OFFSETS for Function 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define AMBASE 0x48 /* AMB Mem Mapped Reg Region Base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MAXCH 0x56 /* Max Channel Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MAXDIMMPERCH 0x57 /* Max DIMM PER Channel Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* OFFSETS for Function 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define TOLM 0x6C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define REDMEMB 0x7C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define REC_ECC_LOCATOR_ODD(x) ((x) & 0x3fe00) /* bits [17:9] indicate ODD, [8:0] indicate EVEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MIR0 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MIR1 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define AMIR0 0x8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define AMIR1 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* Fatal error registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define FERR_FAT_FBD 0x98 /* also called as FERR_FAT_FB_DIMM at datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define FERR_FAT_FBDCHAN (3<<28) /* channel index where the highest-order error occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define NERR_FAT_FBD 0x9c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define FERR_NF_FBD 0xa0 /* also called as FERR_NFAT_FB_DIMM at datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Non-fatal error register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define NERR_NF_FBD 0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Enable error mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define EMASK_FBD 0xa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define ERR0_FBD 0xac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define ERR1_FBD 0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define ERR2_FBD 0xb4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MCERR_FBD 0xb8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* No OFFSETS for Device 16 Function 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * Device 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * Function 0: Memory Map Branch 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * Device 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * Function 0: Memory Map Branch 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* OFFSETS for Function 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define AMBPRESENT_0 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define AMBPRESENT_1 0x66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MTR0 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MTR1 0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MTR2 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MTR3 0x86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* OFFSETS for Function 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define NRECFGLOG 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define RECFGLOG 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define NRECMEMA 0xbe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define NRECMEMB 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define NRECFB_DIMMA 0xc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define NRECFB_DIMMB 0xc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define NRECFB_DIMMC 0xcc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define NRECFB_DIMMD 0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define NRECFB_DIMME 0xd4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define NRECFB_DIMMF 0xd8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define REDMEMA 0xdC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define RECMEMA 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define RECMEMB 0xf4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define RECFB_DIMMA 0xf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define RECFB_DIMMB 0xec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define RECFB_DIMMC 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define RECFB_DIMMD 0xf4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define RECFB_DIMME 0xf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define RECFB_DIMMF 0xfC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * Error indicator bits and masks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * Error masks are according with Table 5-17 of i5400 datasheet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) enum error_mask {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) EMASK_M1 = 1<<0, /* Memory Write error on non-redundant retry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) EMASK_M2 = 1<<1, /* Memory or FB-DIMM configuration CRC read error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) EMASK_M3 = 1<<2, /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) EMASK_M4 = 1<<3, /* Uncorrectable Data ECC on Replay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) EMASK_M5 = 1<<4, /* Aliased Uncorrectable Non-Mirrored Demand Data ECC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) EMASK_M6 = 1<<5, /* Unsupported on i5400 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) EMASK_M7 = 1<<6, /* Aliased Uncorrectable Resilver- or Spare-Copy Data ECC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) EMASK_M8 = 1<<7, /* Aliased Uncorrectable Patrol Data ECC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) EMASK_M9 = 1<<8, /* Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) EMASK_M10 = 1<<9, /* Unsupported on i5400 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) EMASK_M11 = 1<<10, /* Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) EMASK_M12 = 1<<11, /* Non-Aliased Uncorrectable Patrol Data ECC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) EMASK_M13 = 1<<12, /* Memory Write error on first attempt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) EMASK_M14 = 1<<13, /* FB-DIMM Configuration Write error on first attempt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) EMASK_M15 = 1<<14, /* Memory or FB-DIMM configuration CRC read error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) EMASK_M16 = 1<<15, /* Channel Failed-Over Occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) EMASK_M17 = 1<<16, /* Correctable Non-Mirrored Demand Data ECC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) EMASK_M18 = 1<<17, /* Unsupported on i5400 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) EMASK_M19 = 1<<18, /* Correctable Resilver- or Spare-Copy Data ECC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) EMASK_M20 = 1<<19, /* Correctable Patrol Data ECC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) EMASK_M21 = 1<<20, /* FB-DIMM Northbound parity error on FB-DIMM Sync Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) EMASK_M22 = 1<<21, /* SPD protocol Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) EMASK_M23 = 1<<22, /* Non-Redundant Fast Reset Timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) EMASK_M24 = 1<<23, /* Refresh error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) EMASK_M25 = 1<<24, /* Memory Write error on redundant retry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) EMASK_M26 = 1<<25, /* Redundant Fast Reset Timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) EMASK_M27 = 1<<26, /* Correctable Counter Threshold Exceeded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) EMASK_M28 = 1<<27, /* DIMM-Spare Copy Completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) EMASK_M29 = 1<<28, /* DIMM-Isolation Completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * Names to translate bit error into something useful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static const char *error_name[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) [0] = "Memory Write error on non-redundant retry",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) [1] = "Memory or FB-DIMM configuration CRC read error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) [3] = "Uncorrectable Data ECC on Replay",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) [4] = "Aliased Uncorrectable Non-Mirrored Demand Data ECC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* M6 Unsupported on i5400 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) [6] = "Aliased Uncorrectable Resilver- or Spare-Copy Data ECC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) [7] = "Aliased Uncorrectable Patrol Data ECC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) [8] = "Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* M10 Unsupported on i5400 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) [10] = "Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) [11] = "Non-Aliased Uncorrectable Patrol Data ECC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) [12] = "Memory Write error on first attempt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) [13] = "FB-DIMM Configuration Write error on first attempt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) [14] = "Memory or FB-DIMM configuration CRC read error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) [15] = "Channel Failed-Over Occurred",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) [16] = "Correctable Non-Mirrored Demand Data ECC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* M18 Unsupported on i5400 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) [18] = "Correctable Resilver- or Spare-Copy Data ECC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) [19] = "Correctable Patrol Data ECC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) [20] = "FB-DIMM Northbound parity error on FB-DIMM Sync Status",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) [21] = "SPD protocol Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) [22] = "Non-Redundant Fast Reset Timeout",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) [23] = "Refresh error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) [24] = "Memory Write error on redundant retry",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) [25] = "Redundant Fast Reset Timeout",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) [26] = "Correctable Counter Threshold Exceeded",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) [27] = "DIMM-Spare Copy Completed",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) [28] = "DIMM-Isolation Completed",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* Fatal errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define ERROR_FAT_MASK (EMASK_M1 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) EMASK_M2 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) EMASK_M23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* Correctable errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define ERROR_NF_CORRECTABLE (EMASK_M27 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) EMASK_M20 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) EMASK_M19 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) EMASK_M18 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) EMASK_M17 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) EMASK_M16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define ERROR_NF_DIMM_SPARE (EMASK_M29 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) EMASK_M28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define ERROR_NF_SPD_PROTOCOL (EMASK_M22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define ERROR_NF_NORTH_CRC (EMASK_M21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* Recoverable errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define ERROR_NF_RECOVERABLE (EMASK_M26 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) EMASK_M25 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) EMASK_M24 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) EMASK_M15 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) EMASK_M14 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) EMASK_M13 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) EMASK_M12 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) EMASK_M11 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) EMASK_M9 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) EMASK_M8 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) EMASK_M7 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) EMASK_M5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* uncorrectable errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define ERROR_NF_UNCORRECTABLE (EMASK_M4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* mask to all non-fatal errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define ERROR_NF_MASK (ERROR_NF_CORRECTABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ERROR_NF_UNCORRECTABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ERROR_NF_RECOVERABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ERROR_NF_DIMM_SPARE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ERROR_NF_SPD_PROTOCOL | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ERROR_NF_NORTH_CRC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * Define error masks for the several registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* Enable all fatal and non fatal errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define ENABLE_EMASK_ALL (ERROR_FAT_MASK | ERROR_NF_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* mask for fatal error registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define FERR_FAT_MASK ERROR_FAT_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* masks for non-fatal error register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static inline int to_nf_mask(unsigned int mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return (mask & EMASK_M29) | (mask >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static inline int from_nf_ferr(unsigned int mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return (mask & EMASK_M29) | /* Bit 28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) (mask & ((1 << 28) - 1) << 3); /* Bits 0 to 27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define FERR_NF_MASK to_nf_mask(ERROR_NF_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define FERR_NF_CORRECTABLE to_nf_mask(ERROR_NF_CORRECTABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define FERR_NF_DIMM_SPARE to_nf_mask(ERROR_NF_DIMM_SPARE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define FERR_NF_SPD_PROTOCOL to_nf_mask(ERROR_NF_SPD_PROTOCOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define FERR_NF_NORTH_CRC to_nf_mask(ERROR_NF_NORTH_CRC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define FERR_NF_RECOVERABLE to_nf_mask(ERROR_NF_RECOVERABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define FERR_NF_UNCORRECTABLE to_nf_mask(ERROR_NF_UNCORRECTABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* Defines to extract the vaious fields from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * MTRx - Memory Technology Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define MTR_DIMMS_PRESENT(mtr) ((mtr) & (1 << 10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define MTR_DIMMS_ETHROTTLE(mtr) ((mtr) & (1 << 9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define MTR_DRAM_WIDTH(mtr) (((mtr) & (1 << 8)) ? 8 : 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define MTR_DRAM_BANKS(mtr) (((mtr) & (1 << 6)) ? 8 : 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define MTR_DRAM_BANKS_ADDR_BITS(mtr) ((MTR_DRAM_BANKS(mtr) == 8) ? 3 : 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define MTR_DIMM_RANK(mtr) (((mtr) >> 5) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define MTR_DIMM_RANK_ADDR_BITS(mtr) (MTR_DIMM_RANK(mtr) ? 2 : 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* This applies to FERR_NF_FB-DIMM as well as FERR_FAT_FB-DIMM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static inline int extract_fbdchan_indx(u32 x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return (x>>28) & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* Device name and register DID (Device ID) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct i5400_dev_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) const char *ctl_name; /* name for this device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u16 fsb_mapping_errors; /* DID for the branchmap,control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* Table of devices attributes supported by this driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static const struct i5400_dev_info i5400_devs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .ctl_name = "I5400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_5400_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct i5400_dimm_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) int megabytes; /* size, 0 means not present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* driver private data structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct i5400_pvt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct pci_dev *system_address; /* 16.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct pci_dev *branchmap_werrors; /* 16.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct pci_dev *fsb_error_regs; /* 16.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct pci_dev *branch_0; /* 21.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct pci_dev *branch_1; /* 22.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u16 tolm; /* top of low memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u64 ambase; /* AMB BAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) u32 ambase_bottom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u32 ambase_top;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) } u __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u16 mir0, mir1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) u16 b0_mtr[DIMMS_PER_CHANNEL]; /* Memory Technlogy Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) u16 b0_ambpresent0; /* Branch 0, Channel 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u16 b0_ambpresent1; /* Brnach 0, Channel 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u16 b1_mtr[DIMMS_PER_CHANNEL]; /* Memory Technlogy Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u16 b1_ambpresent0; /* Branch 1, Channel 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u16 b1_ambpresent1; /* Branch 1, Channel 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* DIMM information matrix, allocating architecture maximums */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct i5400_dimm_info dimm_info[DIMMS_PER_CHANNEL][MAX_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* Actual values for this controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) int maxch; /* Max channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) int maxdimmperch; /* Max DIMMs per channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* I5400 MCH error information retrieved from Hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct i5400_error_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* These registers are always read from the MC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u32 ferr_fat_fbd; /* First Errors Fatal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) u32 nerr_fat_fbd; /* Next Errors Fatal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u32 ferr_nf_fbd; /* First Errors Non-Fatal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) u32 nerr_nf_fbd; /* Next Errors Non-Fatal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* These registers are input ONLY if there was a Recoverable Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u32 redmemb; /* Recoverable Mem Data Error log B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) u16 recmema; /* Recoverable Mem Error log A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) u32 recmemb; /* Recoverable Mem Error log B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* These registers are input ONLY if there was a Non-Rec Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) u16 nrecmema; /* Non-Recoverable Mem log A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) u32 nrecmemb; /* Non-Recoverable Mem log B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* note that nrec_rdwr changed from NRECMEMA to NRECMEMB between the 5000 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 5400 better to use an inline function than a macro in this case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static inline int nrec_bank(struct i5400_error_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return ((info->nrecmema) >> 12) & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static inline int nrec_rank(struct i5400_error_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return ((info->nrecmema) >> 8) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static inline int nrec_buf_id(struct i5400_error_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return ((info->nrecmema)) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static inline int nrec_rdwr(struct i5400_error_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return (info->nrecmemb) >> 31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* This applies to both NREC and REC string so it can be used with nrec_rdwr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) and rec_rdwr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static inline const char *rdwr_str(int rdwr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return rdwr ? "Write" : "Read";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static inline int nrec_cas(struct i5400_error_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return ((info->nrecmemb) >> 16) & 0x1fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static inline int nrec_ras(struct i5400_error_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return (info->nrecmemb) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static inline int rec_bank(struct i5400_error_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return ((info->recmema) >> 12) & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static inline int rec_rank(struct i5400_error_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return ((info->recmema) >> 8) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static inline int rec_rdwr(struct i5400_error_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return (info->recmemb) >> 31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static inline int rec_cas(struct i5400_error_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return ((info->recmemb) >> 16) & 0x1fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static inline int rec_ras(struct i5400_error_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return (info->recmemb) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static struct edac_pci_ctl_info *i5400_pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * i5400_get_error_info Retrieve the hardware error information from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * the hardware and cache it in the 'info'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static void i5400_get_error_info(struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct i5400_error_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct i5400_pvt *pvt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) pvt = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* read in the 1st FATAL error register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) pci_read_config_dword(pvt->branchmap_werrors, FERR_FAT_FBD, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* Mask only the bits that the doc says are valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) value &= (FERR_FAT_FBDCHAN | FERR_FAT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* If there is an error, then read in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) NEXT FATAL error register and the Memory Error Log Register A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (value & FERR_FAT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) info->ferr_fat_fbd = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* harvest the various error data we need */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) pci_read_config_dword(pvt->branchmap_werrors,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) NERR_FAT_FBD, &info->nerr_fat_fbd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) pci_read_config_word(pvt->branchmap_werrors,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) NRECMEMA, &info->nrecmema);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) pci_read_config_dword(pvt->branchmap_werrors,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) NRECMEMB, &info->nrecmemb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* Clear the error bits, by writing them back */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) pci_write_config_dword(pvt->branchmap_werrors,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) FERR_FAT_FBD, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) info->ferr_fat_fbd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) info->nerr_fat_fbd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) info->nrecmema = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) info->nrecmemb = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* read in the 1st NON-FATAL error register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) pci_read_config_dword(pvt->branchmap_werrors, FERR_NF_FBD, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* If there is an error, then read in the 1st NON-FATAL error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * register as well */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (value & FERR_NF_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) info->ferr_nf_fbd = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* harvest the various error data we need */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) pci_read_config_dword(pvt->branchmap_werrors,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) NERR_NF_FBD, &info->nerr_nf_fbd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) pci_read_config_word(pvt->branchmap_werrors,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) RECMEMA, &info->recmema);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) pci_read_config_dword(pvt->branchmap_werrors,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) RECMEMB, &info->recmemb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) pci_read_config_dword(pvt->branchmap_werrors,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) REDMEMB, &info->redmemb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* Clear the error bits, by writing them back */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) pci_write_config_dword(pvt->branchmap_werrors,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) FERR_NF_FBD, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) info->ferr_nf_fbd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) info->nerr_nf_fbd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) info->recmema = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) info->recmemb = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) info->redmemb = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * i5400_proccess_non_recoverable_info(struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * struct i5400_error_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * int handle_errors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * handle the Intel FATAL and unrecoverable errors, if any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static void i5400_proccess_non_recoverable_info(struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct i5400_error_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) unsigned long allErrors)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) char msg[EDAC_MC_LABEL_LEN + 1 + 90 + 80];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) int branch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) int channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) int bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) int buf_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) int rank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) int rdwr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) int ras, cas;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) int errnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) char *type = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) enum hw_event_mc_err_type tp_event = HW_EVENT_ERR_UNCORRECTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (!allErrors)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return; /* if no error, return now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (allErrors & ERROR_FAT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) type = "FATAL";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) tp_event = HW_EVENT_ERR_FATAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) } else if (allErrors & FERR_NF_UNCORRECTABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) type = "NON-FATAL uncorrected";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) type = "NON-FATAL recoverable";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* ONLY ONE of the possible error bits will be set, as per the docs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) branch = extract_fbdchan_indx(info->ferr_fat_fbd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) channel = branch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /* Use the NON-Recoverable macros to extract data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) bank = nrec_bank(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) rank = nrec_rank(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) buf_id = nrec_buf_id(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) rdwr = nrec_rdwr(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) ras = nrec_ras(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) cas = nrec_cas(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) edac_dbg(0, "\t\t%s DIMM= %d Channels= %d,%d (Branch= %d DRAM Bank= %d Buffer ID = %d rdwr= %s ras= %d cas= %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) type, rank, channel, channel + 1, branch >> 1, bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) buf_id, rdwr_str(rdwr), ras, cas);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /* Only 1 bit will be on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /* Form out message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) snprintf(msg, sizeof(msg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) "Bank=%d Buffer ID = %d RAS=%d CAS=%d Err=0x%lx (%s)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) bank, buf_id, ras, cas, allErrors, error_name[errnum]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) edac_mc_handle_error(tp_event, mci, 1, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) branch >> 1, -1, rank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) rdwr ? "Write error" : "Read error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * i5400_process_fatal_error_info(struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * struct i5400_error_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * int handle_errors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * handle the Intel NON-FATAL errors, if any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static void i5400_process_nonfatal_error_info(struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) struct i5400_error_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) char msg[EDAC_MC_LABEL_LEN + 1 + 90 + 80];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) unsigned long allErrors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) int branch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) int channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) int bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) int rank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) int rdwr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) int ras, cas;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) int errnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* mask off the Error bits that are possible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) allErrors = from_nf_ferr(info->ferr_nf_fbd & FERR_NF_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (!allErrors)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return; /* if no error, return now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* ONLY ONE of the possible error bits will be set, as per the docs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (allErrors & (ERROR_NF_UNCORRECTABLE | ERROR_NF_RECOVERABLE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) i5400_proccess_non_recoverable_info(mci, info, allErrors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /* Correctable errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (allErrors & ERROR_NF_CORRECTABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) edac_dbg(0, "\tCorrected bits= 0x%lx\n", allErrors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) branch = extract_fbdchan_indx(info->ferr_nf_fbd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) channel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (REC_ECC_LOCATOR_ODD(info->redmemb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) channel = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) /* Convert channel to be based from zero, instead of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * from branch base of 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) channel += branch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) bank = rec_bank(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) rank = rec_rank(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) rdwr = rec_rdwr(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) ras = rec_ras(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) cas = rec_cas(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /* Only 1 bit will be on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) edac_dbg(0, "\t\tDIMM= %d Channel= %d (Branch %d DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) rank, channel, branch >> 1, bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) rdwr_str(rdwr), ras, cas);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /* Form out message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) snprintf(msg, sizeof(msg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) "Corrected error (Branch=%d DRAM-Bank=%d RDWR=%s "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) "RAS=%d CAS=%d, CE Err=0x%lx (%s))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) branch >> 1, bank, rdwr_str(rdwr), ras, cas,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) allErrors, error_name[errnum]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) branch >> 1, channel % 2, rank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) rdwr ? "Write error" : "Read error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) /* Miscellaneous errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) branch = extract_fbdchan_indx(info->ferr_nf_fbd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) i5400_mc_printk(mci, KERN_EMERG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) "Non-Fatal misc error (Branch=%d Err=%#lx (%s))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) branch >> 1, allErrors, error_name[errnum]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * i5400_process_error_info Process the error info that is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * in the 'info' structure, previously retrieved from hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static void i5400_process_error_info(struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) struct i5400_error_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) { u32 allErrors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /* First handle any fatal errors that occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) allErrors = (info->ferr_fat_fbd & FERR_FAT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) i5400_proccess_non_recoverable_info(mci, info, allErrors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /* now handle any non-fatal errors that occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) i5400_process_nonfatal_error_info(mci, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * i5400_clear_error Retrieve any error from the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) * but do NOT process that error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * Used for 'clearing' out of previous errors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * Called by the Core module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static void i5400_clear_error(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) struct i5400_error_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) i5400_get_error_info(mci, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * i5400_check_error Retrieve and process errors reported by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) * hardware. Called by the Core module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) static void i5400_check_error(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) struct i5400_error_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) edac_dbg(4, "MC%d\n", mci->mc_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) i5400_get_error_info(mci, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) i5400_process_error_info(mci, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) * i5400_put_devices 'put' all the devices that we have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) * reserved via 'get'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static void i5400_put_devices(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) struct i5400_pvt *pvt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) pvt = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /* Decrement usage count for devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) pci_dev_put(pvt->branch_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) pci_dev_put(pvt->branch_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) pci_dev_put(pvt->fsb_error_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) pci_dev_put(pvt->branchmap_werrors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) * i5400_get_devices Find and perform 'get' operation on the MCH's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) * device/functions we want to reference for this driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * Need to 'get' device 16 func 1 and func 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static int i5400_get_devices(struct mem_ctl_info *mci, int dev_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) struct i5400_pvt *pvt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) pvt = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) pvt->branchmap_werrors = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) pvt->fsb_error_regs = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) pvt->branch_0 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) pvt->branch_1 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) /* Attempt to 'get' the MCH register we want */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) pdev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) PCI_DEVICE_ID_INTEL_5400_ERR, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (!pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /* End of list, leave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) i5400_printk(KERN_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) "'system address,Process Bus' "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) "device not found:"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) "vendor 0x%x device 0x%x ERR func 1 "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) "(broken BIOS?)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) PCI_VENDOR_ID_INTEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) PCI_DEVICE_ID_INTEL_5400_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) /* Store device 16 func 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (PCI_FUNC(pdev->devfn) == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) pvt->branchmap_werrors = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) pdev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) PCI_DEVICE_ID_INTEL_5400_ERR, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (!pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /* End of list, leave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) i5400_printk(KERN_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) "'system address,Process Bus' "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) "device not found:"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) "vendor 0x%x device 0x%x ERR func 2 "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) "(broken BIOS?)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) PCI_VENDOR_ID_INTEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) PCI_DEVICE_ID_INTEL_5400_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) pci_dev_put(pvt->branchmap_werrors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) /* Store device 16 func 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (PCI_FUNC(pdev->devfn) == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) pvt->fsb_error_regs = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) edac_dbg(1, "System Address, processor bus- PCI Bus ID: %s %x:%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) pci_name(pvt->system_address),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) pvt->system_address->vendor, pvt->system_address->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) edac_dbg(1, "Branchmap, control and errors - PCI Bus ID: %s %x:%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) pci_name(pvt->branchmap_werrors),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) pvt->branchmap_werrors->vendor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) pvt->branchmap_werrors->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) edac_dbg(1, "FSB Error Regs - PCI Bus ID: %s %x:%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) pci_name(pvt->fsb_error_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) pvt->fsb_error_regs->vendor, pvt->fsb_error_regs->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) pvt->branch_0 = pci_get_device(PCI_VENDOR_ID_INTEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) PCI_DEVICE_ID_INTEL_5400_FBD0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (!pvt->branch_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) i5400_printk(KERN_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) "MC: 'BRANCH 0' device not found:"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) "vendor 0x%x device 0x%x Func 0 (broken BIOS?)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5400_FBD0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) pci_dev_put(pvt->fsb_error_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) pci_dev_put(pvt->branchmap_werrors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) /* If this device claims to have more than 2 channels then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) * fetch Branch 1's information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) if (pvt->maxch < CHANNELS_PER_BRANCH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) pvt->branch_1 = pci_get_device(PCI_VENDOR_ID_INTEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) PCI_DEVICE_ID_INTEL_5400_FBD1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (!pvt->branch_1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) i5400_printk(KERN_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) "MC: 'BRANCH 1' device not found:"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) "vendor 0x%x device 0x%x Func 0 "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) "(broken BIOS?)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) PCI_VENDOR_ID_INTEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) PCI_DEVICE_ID_INTEL_5400_FBD1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) pci_dev_put(pvt->branch_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) pci_dev_put(pvt->fsb_error_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) pci_dev_put(pvt->branchmap_werrors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) * determine_amb_present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) * the information is contained in DIMMS_PER_CHANNEL different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) * registers determining which of the DIMMS_PER_CHANNEL requires
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) * knowing which channel is in question
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) * 2 branches, each with 2 channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) * b0_ambpresent0 for channel '0'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) * b0_ambpresent1 for channel '1'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) * b1_ambpresent0 for channel '2'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) * b1_ambpresent1 for channel '3'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) static int determine_amb_present_reg(struct i5400_pvt *pvt, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) int amb_present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) if (channel < CHANNELS_PER_BRANCH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (channel & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) amb_present = pvt->b0_ambpresent1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) amb_present = pvt->b0_ambpresent0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (channel & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) amb_present = pvt->b1_ambpresent1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) amb_present = pvt->b1_ambpresent0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return amb_present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) * determine_mtr(pvt, dimm, channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) * return the proper MTR register as determine by the dimm and desired channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) static int determine_mtr(struct i5400_pvt *pvt, int dimm, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) int mtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) int n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) /* There is one MTR for each slot pair of FB-DIMMs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) Each slot pair may be at branch 0 or branch 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) n = dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (n >= DIMMS_PER_CHANNEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) edac_dbg(0, "ERROR: trying to access an invalid dimm: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) dimm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) if (channel < CHANNELS_PER_BRANCH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) mtr = pvt->b0_mtr[n];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) mtr = pvt->b1_mtr[n];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) return mtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) static void decode_mtr(int slot_row, u16 mtr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) int ans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) ans = MTR_DIMMS_PRESENT(mtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) edac_dbg(2, "\tMTR%d=0x%x: DIMMs are %sPresent\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) slot_row, mtr, ans ? "" : "NOT ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) if (!ans)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) edac_dbg(2, "\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) edac_dbg(2, "\t\tELECTRICAL THROTTLING is %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) MTR_DIMMS_ETHROTTLE(mtr) ? "enabled" : "disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) edac_dbg(2, "\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) edac_dbg(2, "\t\tNUMRANK: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) MTR_DIMM_RANK(mtr) ? "double" : "single");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) edac_dbg(2, "\t\tNUMROW: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) MTR_DIMM_ROWS(mtr) == 0 ? "8,192 - 13 rows" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) MTR_DIMM_ROWS(mtr) == 1 ? "16,384 - 14 rows" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) MTR_DIMM_ROWS(mtr) == 2 ? "32,768 - 15 rows" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) "65,536 - 16 rows");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) edac_dbg(2, "\t\tNUMCOL: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) MTR_DIMM_COLS(mtr) == 0 ? "1,024 - 10 columns" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) MTR_DIMM_COLS(mtr) == 1 ? "2,048 - 11 columns" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) MTR_DIMM_COLS(mtr) == 2 ? "4,096 - 12 columns" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) "reserved");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) static void handle_channel(struct i5400_pvt *pvt, int dimm, int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) struct i5400_dimm_info *dinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) int mtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) int amb_present_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) int addrBits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) mtr = determine_mtr(pvt, dimm, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (MTR_DIMMS_PRESENT(mtr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) amb_present_reg = determine_amb_present_reg(pvt, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) /* Determine if there is a DIMM present in this DIMM slot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (amb_present_reg & (1 << dimm)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) /* Start with the number of bits for a Bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) * on the DRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) addrBits = MTR_DRAM_BANKS_ADDR_BITS(mtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) /* Add thenumber of ROW bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) /* add the number of COLUMN bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) /* add the number of RANK bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) addrBits += MTR_DIMM_RANK(mtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) addrBits += 6; /* add 64 bits per DIMM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) addrBits -= 20; /* divide by 2^^20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) addrBits -= 3; /* 8 bits per bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) dinfo->megabytes = 1 << addrBits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) * calculate_dimm_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) * also will output a DIMM matrix map, if debug is enabled, for viewing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) * how the DIMMs are populated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) static void calculate_dimm_size(struct i5400_pvt *pvt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) struct i5400_dimm_info *dinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) int dimm, max_dimms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) char *p, *mem_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) int space, n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) int channel, branch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) /* ================= Generate some debug output ================= */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) space = PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) mem_buffer = p = kmalloc(space, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) if (p == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) i5400_printk(KERN_ERR, "MC: %s:%s() kmalloc() failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) __FILE__, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) /* Scan all the actual DIMMS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) * and calculate the information for each DIMM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) * Start with the highest dimm first, to display it first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) * and work toward the 0th dimm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) max_dimms = pvt->maxdimmperch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) for (dimm = max_dimms - 1; dimm >= 0; dimm--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) /* on an odd dimm, first output a 'boundary' marker,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) * then reset the message buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) if (dimm & 0x1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) n = snprintf(p, space, "---------------------------"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) "-------------------------------");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) p += n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) space -= n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) edac_dbg(2, "%s\n", mem_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) p = mem_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) space = PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) n = snprintf(p, space, "dimm %2d ", dimm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) p += n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) space -= n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) for (channel = 0; channel < pvt->maxch; channel++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) dinfo = &pvt->dimm_info[dimm][channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) handle_channel(pvt, dimm, channel, dinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) n = snprintf(p, space, "%4d MB | ", dinfo->megabytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) p += n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) space -= n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) edac_dbg(2, "%s\n", mem_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) p = mem_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) space = PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) /* Output the last bottom 'boundary' marker */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) n = snprintf(p, space, "---------------------------"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) "-------------------------------");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) p += n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) space -= n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) edac_dbg(2, "%s\n", mem_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) p = mem_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) space = PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) /* now output the 'channel' labels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) n = snprintf(p, space, " ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) p += n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) space -= n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) for (channel = 0; channel < pvt->maxch; channel++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) n = snprintf(p, space, "channel %d | ", channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) p += n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) space -= n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) space -= n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) edac_dbg(2, "%s\n", mem_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) p = mem_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) space = PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) n = snprintf(p, space, " ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) p += n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) for (branch = 0; branch < MAX_BRANCHES; branch++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) n = snprintf(p, space, " branch %d | ", branch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) p += n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) space -= n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) /* output the last message and free buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) edac_dbg(2, "%s\n", mem_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) kfree(mem_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) * i5400_get_mc_regs read in the necessary registers and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) * cache locally
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) * Fills in the private data members
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) static void i5400_get_mc_regs(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) struct i5400_pvt *pvt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) u32 actual_tolm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) u16 limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) int slot_row;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) int way0, way1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) pvt = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) pci_read_config_dword(pvt->system_address, AMBASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) &pvt->u.ambase_bottom);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) pci_read_config_dword(pvt->system_address, AMBASE + sizeof(u32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) &pvt->u.ambase_top);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) edac_dbg(2, "AMBASE= 0x%lx MAXCH= %d MAX-DIMM-Per-CH= %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) (long unsigned int)pvt->ambase, pvt->maxch, pvt->maxdimmperch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) /* Get the Branch Map regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) pci_read_config_word(pvt->branchmap_werrors, TOLM, &pvt->tolm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) pvt->tolm >>= 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) edac_dbg(2, "\nTOLM (number of 256M regions) =%u (0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) pvt->tolm, pvt->tolm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) actual_tolm = (u32) ((1000l * pvt->tolm) >> (30 - 28));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) edac_dbg(2, "Actual TOLM byte addr=%u.%03u GB (0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) actual_tolm/1000, actual_tolm % 1000, pvt->tolm << 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) pci_read_config_word(pvt->branchmap_werrors, MIR0, &pvt->mir0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) pci_read_config_word(pvt->branchmap_werrors, MIR1, &pvt->mir1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) /* Get the MIR[0-1] regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) limit = (pvt->mir0 >> 4) & 0x0fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) way0 = pvt->mir0 & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) way1 = pvt->mir0 & 0x2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) edac_dbg(2, "MIR0: limit= 0x%x WAY1= %u WAY0= %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) limit, way1, way0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) limit = (pvt->mir1 >> 4) & 0xfff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) way0 = pvt->mir1 & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) way1 = pvt->mir1 & 0x2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) edac_dbg(2, "MIR1: limit= 0x%x WAY1= %u WAY0= %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) limit, way1, way0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) /* Get the set of MTR[0-3] regs by each branch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) for (slot_row = 0; slot_row < DIMMS_PER_CHANNEL; slot_row++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) int where = MTR0 + (slot_row * sizeof(u16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) /* Branch 0 set of MTR registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) pci_read_config_word(pvt->branch_0, where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) &pvt->b0_mtr[slot_row]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) edac_dbg(2, "MTR%d where=0x%x B0 value=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) slot_row, where, pvt->b0_mtr[slot_row]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) if (pvt->maxch < CHANNELS_PER_BRANCH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) pvt->b1_mtr[slot_row] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) /* Branch 1 set of MTR registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) pci_read_config_word(pvt->branch_1, where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) &pvt->b1_mtr[slot_row]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) edac_dbg(2, "MTR%d where=0x%x B1 value=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) slot_row, where, pvt->b1_mtr[slot_row]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) /* Read and dump branch 0's MTRs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) edac_dbg(2, "Memory Technology Registers:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) edac_dbg(2, " Branch 0:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) for (slot_row = 0; slot_row < DIMMS_PER_CHANNEL; slot_row++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) decode_mtr(slot_row, pvt->b0_mtr[slot_row]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) pci_read_config_word(pvt->branch_0, AMBPRESENT_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) &pvt->b0_ambpresent0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) edac_dbg(2, "\t\tAMB-Branch 0-present0 0x%x:\n", pvt->b0_ambpresent0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) pci_read_config_word(pvt->branch_0, AMBPRESENT_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) &pvt->b0_ambpresent1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) edac_dbg(2, "\t\tAMB-Branch 0-present1 0x%x:\n", pvt->b0_ambpresent1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) /* Only if we have 2 branchs (4 channels) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) if (pvt->maxch < CHANNELS_PER_BRANCH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) pvt->b1_ambpresent0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) pvt->b1_ambpresent1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) /* Read and dump branch 1's MTRs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) edac_dbg(2, " Branch 1:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) for (slot_row = 0; slot_row < DIMMS_PER_CHANNEL; slot_row++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) decode_mtr(slot_row, pvt->b1_mtr[slot_row]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) pci_read_config_word(pvt->branch_1, AMBPRESENT_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) &pvt->b1_ambpresent0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) edac_dbg(2, "\t\tAMB-Branch 1-present0 0x%x:\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) pvt->b1_ambpresent0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) pci_read_config_word(pvt->branch_1, AMBPRESENT_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) &pvt->b1_ambpresent1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) edac_dbg(2, "\t\tAMB-Branch 1-present1 0x%x:\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) pvt->b1_ambpresent1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) /* Go and determine the size of each DIMM and place in an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) * orderly matrix */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) calculate_dimm_size(pvt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) * i5400_init_dimms Initialize the 'dimms' table within
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) * the mci control structure with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) * addressing of memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) * return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) * 0 success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) * 1 no actual memory found on this MC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) static int i5400_init_dimms(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) struct i5400_pvt *pvt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) struct dimm_info *dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) int ndimms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) int mtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) int size_mb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) int channel, slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) pvt = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) ndimms = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) * FIXME: remove pvt->dimm_info[slot][channel] and use the 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) * layers here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) for (channel = 0; channel < mci->layers[0].size * mci->layers[1].size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) channel++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) for (slot = 0; slot < mci->layers[2].size; slot++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) mtr = determine_mtr(pvt, slot, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) /* if no DIMMS on this slot, continue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) if (!MTR_DIMMS_PRESENT(mtr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) dimm = edac_get_dimm(mci, channel / 2, channel % 2, slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) size_mb = pvt->dimm_info[slot][channel].megabytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) edac_dbg(2, "dimm (branch %d channel %d slot %d): %d.%03d GB\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) channel / 2, channel % 2, slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) size_mb / 1000, size_mb % 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) dimm->nr_pages = size_mb << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) dimm->grain = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) dimm->dtype = MTR_DRAM_WIDTH(mtr) == 8 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) DEV_X8 : DEV_X4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) dimm->mtype = MEM_FB_DDR2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) * The eccc mechanism is SDDC (aka SECC), with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) * is similar to Chipkill.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) dimm->edac_mode = MTR_DRAM_WIDTH(mtr) == 8 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) EDAC_S8ECD8ED : EDAC_S4ECD4ED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) ndimms++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) * When just one memory is provided, it should be at location (0,0,0).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) * With such single-DIMM mode, the SDCC algorithm degrades to SECDEC+.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) if (ndimms == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) mci->dimms[0]->edac_mode = EDAC_SECDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) return (ndimms == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) * i5400_enable_error_reporting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) * Turn on the memory reporting features of the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) static void i5400_enable_error_reporting(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) struct i5400_pvt *pvt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) u32 fbd_error_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) pvt = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) /* Read the FBD Error Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) pci_read_config_dword(pvt->branchmap_werrors, EMASK_FBD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) &fbd_error_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) /* Enable with a '0' */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) fbd_error_mask &= ~(ENABLE_EMASK_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) pci_write_config_dword(pvt->branchmap_werrors, EMASK_FBD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) fbd_error_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) * i5400_probe1 Probe for ONE instance of device to see if it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) * present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) * return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) * 0 for FOUND a device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) * < 0 for error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) static int i5400_probe1(struct pci_dev *pdev, int dev_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) struct mem_ctl_info *mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) struct i5400_pvt *pvt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) struct edac_mc_layer layers[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) if (dev_idx >= ARRAY_SIZE(i5400_devs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) edac_dbg(0, "MC: pdev bus %u dev=0x%x fn=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) pdev->bus->number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) /* We only are looking for func 0 of the set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) if (PCI_FUNC(pdev->devfn) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) * allocate a new MC control structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) * This drivers uses the DIMM slot as "csrow" and the rest as "channel".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) layers[0].type = EDAC_MC_LAYER_BRANCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) layers[0].size = MAX_BRANCHES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) layers[0].is_virt_csrow = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) layers[1].type = EDAC_MC_LAYER_CHANNEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) layers[1].size = CHANNELS_PER_BRANCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) layers[1].is_virt_csrow = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) layers[2].type = EDAC_MC_LAYER_SLOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) layers[2].size = DIMMS_PER_CHANNEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) layers[2].is_virt_csrow = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) if (mci == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) edac_dbg(0, "MC: mci = %p\n", mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) mci->pdev = &pdev->dev; /* record ptr to the generic device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) pvt = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) pvt->system_address = pdev; /* Record this device in our private */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) pvt->maxch = MAX_CHANNELS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) pvt->maxdimmperch = DIMMS_PER_CHANNEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) /* 'get' the pci devices we want to reserve for our use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) if (i5400_get_devices(mci, dev_idx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) goto fail0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) /* Time to get serious */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) i5400_get_mc_regs(mci); /* retrieve the hardware registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) mci->mc_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) mci->mtype_cap = MEM_FLAG_FB_DDR2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) mci->edac_ctl_cap = EDAC_FLAG_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) mci->edac_cap = EDAC_FLAG_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) mci->mod_name = "i5400_edac.c";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) mci->ctl_name = i5400_devs[dev_idx].ctl_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) mci->dev_name = pci_name(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) mci->ctl_page_to_phys = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) /* Set the function pointer to an actual operation function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) mci->edac_check = i5400_check_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) /* initialize the MC control structure 'dimms' table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) * with the mapping and control information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) if (i5400_init_dimms(mci)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) edac_dbg(0, "MC: Setting mci->edac_cap to EDAC_FLAG_NONE because i5400_init_dimms() returned nonzero value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) mci->edac_cap = EDAC_FLAG_NONE; /* no dimms found */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) edac_dbg(1, "MC: Enable error reporting now\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) i5400_enable_error_reporting(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) /* add this new MC control structure to EDAC's list of MCs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) if (edac_mc_add_mc(mci)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) /* FIXME: perhaps some code should go here that disables error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) * reporting if we just enabled it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) goto fail1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) i5400_clear_error(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) /* allocating generic PCI control info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) i5400_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) if (!i5400_pci) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) "%s(): Unable to create PCI control\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) "%s(): PCI error report via EDAC not setup\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) /* Error exit unwinding stack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) fail1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) i5400_put_devices(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) fail0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) * i5400_init_one constructor for one instance of device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) * returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) * negative on error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) * count (>= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) static int i5400_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) edac_dbg(0, "MC:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) /* wake up device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) rc = pci_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) /* now probe and enable the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) return i5400_probe1(pdev, id->driver_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) * i5400_remove_one destructor for one instance of device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) static void i5400_remove_one(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) struct mem_ctl_info *mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) edac_dbg(0, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) if (i5400_pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) edac_pci_release_generic_ctl(i5400_pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) mci = edac_mc_del_mc(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) if (!mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) /* retrieve references to resources, and free those resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) i5400_put_devices(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) * pci_device_id table for which devices we are looking for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) * The "E500P" device is the first device supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) static const struct pci_device_id i5400_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5400_ERR)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) {0,} /* 0 terminated list. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) MODULE_DEVICE_TABLE(pci, i5400_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) * i5400_driver pci_driver structure for this module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) static struct pci_driver i5400_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) .name = "i5400_edac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) .probe = i5400_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) .remove = i5400_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) .id_table = i5400_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) * i5400_init Module entry function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) * Try to initialize this module for its devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) static int __init i5400_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) int pci_rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) edac_dbg(2, "MC:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) /* Ensure that the OPSTATE is set correctly for POLL or NMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) opstate_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) pci_rc = pci_register_driver(&i5400_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) return (pci_rc < 0) ? pci_rc : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) * i5400_exit() Module exit function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) * Unregister the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) static void __exit i5400_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) edac_dbg(2, "MC:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) pci_unregister_driver(&i5400_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) module_init(i5400_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) module_exit(i5400_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) MODULE_AUTHOR("Ben Woodard <woodard@redhat.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) MODULE_AUTHOR("Mauro Carvalho Chehab");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) MODULE_AUTHOR("Red Hat Inc. (https://www.redhat.com)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) MODULE_DESCRIPTION("MC Driver for Intel I5400 memory controllers - "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) I5400_REVISION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) module_param(edac_op_state, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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