^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Intel 5100 Memory Controllers kernel module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This file may be distributed under the terms of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * GNU General Public License.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This module is based on the following document:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Intel 5100X Chipset Memory Controller Hub (MCH) - Datasheet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * http://download.intel.com/design/chipsets/datashts/318378.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * The intel 5100 has two independent channels. EDAC core currently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * can not reflect this configuration so instead the chip-select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * rows for each respective channel are laid out one after another,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * the first half belonging to channel 0, the second half belonging
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * to channel 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * This driver is for DDR2 DIMMs, and it uses chip select to select among the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * several ranks. However, instead of showing memories as ranks, it outputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * them as DIMM's. An internal table creates the association between ranks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * and DIMM's.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/pci_ids.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/edac.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/mmzone.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "edac_module.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* register addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* device 16, func 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define I5100_MC 0x40 /* Memory Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define I5100_MC_SCRBEN_MASK (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define I5100_MC_SCRBDONE_MASK (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define I5100_MS 0x44 /* Memory Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define I5100_SPDDATA 0x48 /* Serial Presence Detect Status Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define I5100_SPDCMD 0x4c /* Serial Presence Detect Command Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define I5100_TOLM 0x6c /* Top of Low Memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define I5100_MIR0 0x80 /* Memory Interleave Range 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define I5100_MIR1 0x84 /* Memory Interleave Range 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define I5100_AMIR_0 0x8c /* Adjusted Memory Interleave Range 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define I5100_AMIR_1 0x90 /* Adjusted Memory Interleave Range 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define I5100_FERR_NF_MEM 0xa0 /* MC First Non Fatal Errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define I5100_FERR_NF_MEM_M16ERR_MASK (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define I5100_FERR_NF_MEM_M15ERR_MASK (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define I5100_FERR_NF_MEM_M14ERR_MASK (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define I5100_FERR_NF_MEM_M12ERR_MASK (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define I5100_FERR_NF_MEM_M11ERR_MASK (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define I5100_FERR_NF_MEM_M10ERR_MASK (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define I5100_FERR_NF_MEM_M6ERR_MASK (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define I5100_FERR_NF_MEM_M5ERR_MASK (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define I5100_FERR_NF_MEM_M4ERR_MASK (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define I5100_FERR_NF_MEM_M1ERR_MASK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define I5100_FERR_NF_MEM_ANY_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) (I5100_FERR_NF_MEM_M16ERR_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) I5100_FERR_NF_MEM_M15ERR_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) I5100_FERR_NF_MEM_M14ERR_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) I5100_FERR_NF_MEM_M12ERR_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) I5100_FERR_NF_MEM_M11ERR_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) I5100_FERR_NF_MEM_M10ERR_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) I5100_FERR_NF_MEM_M6ERR_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) I5100_FERR_NF_MEM_M5ERR_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) I5100_FERR_NF_MEM_M4ERR_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) I5100_FERR_NF_MEM_M1ERR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define I5100_NERR_NF_MEM 0xa4 /* MC Next Non-Fatal Errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define I5100_EMASK_MEM 0xa8 /* MC Error Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define I5100_MEM0EINJMSK0 0x200 /* Injection Mask0 Register Channel 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define I5100_MEM1EINJMSK0 0x208 /* Injection Mask0 Register Channel 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define I5100_MEMXEINJMSK0_EINJEN (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define I5100_MEM0EINJMSK1 0x204 /* Injection Mask1 Register Channel 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define I5100_MEM1EINJMSK1 0x206 /* Injection Mask1 Register Channel 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* Device 19, Function 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define I5100_DINJ0 0x9a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* device 21 and 22, func 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define I5100_MTR_0 0x154 /* Memory Technology Registers 0-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define I5100_DMIR 0x15c /* DIMM Interleave Range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define I5100_VALIDLOG 0x18c /* Valid Log Markers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define I5100_NRECMEMA 0x190 /* Non-Recoverable Memory Error Log Reg A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define I5100_NRECMEMB 0x194 /* Non-Recoverable Memory Error Log Reg B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define I5100_REDMEMA 0x198 /* Recoverable Memory Data Error Log Reg A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define I5100_REDMEMB 0x19c /* Recoverable Memory Data Error Log Reg B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define I5100_RECMEMA 0x1a0 /* Recoverable Memory Error Log Reg A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define I5100_RECMEMB 0x1a4 /* Recoverable Memory Error Log Reg B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define I5100_MTR_4 0x1b0 /* Memory Technology Registers 4,5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* bit field accessors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static inline u32 i5100_mc_scrben(u32 mc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return mc >> 7 & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static inline u32 i5100_mc_errdeten(u32 mc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return mc >> 5 & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static inline u32 i5100_mc_scrbdone(u32 mc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return mc >> 4 & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static inline u16 i5100_spddata_rdo(u16 a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return a >> 15 & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static inline u16 i5100_spddata_sbe(u16 a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return a >> 13 & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static inline u16 i5100_spddata_busy(u16 a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return a >> 12 & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static inline u16 i5100_spddata_data(u16 a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return a & ((1 << 8) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static inline u32 i5100_spdcmd_create(u32 dti, u32 ckovrd, u32 sa, u32 ba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 data, u32 cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return ((dti & ((1 << 4) - 1)) << 28) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ((ckovrd & 1) << 27) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ((sa & ((1 << 3) - 1)) << 24) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ((ba & ((1 << 8) - 1)) << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ((data & ((1 << 8) - 1)) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) (cmd & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static inline u16 i5100_tolm_tolm(u16 a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return a >> 12 & ((1 << 4) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static inline u16 i5100_mir_limit(u16 a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return a >> 4 & ((1 << 12) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static inline u16 i5100_mir_way1(u16 a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return a >> 1 & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static inline u16 i5100_mir_way0(u16 a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return a & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static inline u32 i5100_ferr_nf_mem_chan_indx(u32 a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return a >> 28 & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static inline u32 i5100_ferr_nf_mem_any(u32 a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return a & I5100_FERR_NF_MEM_ANY_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static inline u32 i5100_nerr_nf_mem_any(u32 a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return i5100_ferr_nf_mem_any(a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static inline u32 i5100_dmir_limit(u32 a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return a >> 16 & ((1 << 11) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static inline u32 i5100_dmir_rank(u32 a, u32 i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return a >> (4 * i) & ((1 << 2) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static inline u16 i5100_mtr_present(u16 a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return a >> 10 & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static inline u16 i5100_mtr_ethrottle(u16 a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return a >> 9 & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static inline u16 i5100_mtr_width(u16 a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return a >> 8 & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static inline u16 i5100_mtr_numbank(u16 a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return a >> 6 & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static inline u16 i5100_mtr_numrow(u16 a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return a >> 2 & ((1 << 2) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static inline u16 i5100_mtr_numcol(u16 a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return a & ((1 << 2) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static inline u32 i5100_validlog_redmemvalid(u32 a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return a >> 2 & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static inline u32 i5100_validlog_recmemvalid(u32 a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return a >> 1 & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static inline u32 i5100_validlog_nrecmemvalid(u32 a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return a & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static inline u32 i5100_nrecmema_merr(u32 a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return a >> 15 & ((1 << 5) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static inline u32 i5100_nrecmema_bank(u32 a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return a >> 12 & ((1 << 3) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static inline u32 i5100_nrecmema_rank(u32 a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return a >> 8 & ((1 << 3) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static inline u32 i5100_nrecmema_dm_buf_id(u32 a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return a & ((1 << 8) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static inline u32 i5100_nrecmemb_cas(u32 a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return a >> 16 & ((1 << 13) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static inline u32 i5100_nrecmemb_ras(u32 a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return a & ((1 << 16) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static inline u32 i5100_recmema_merr(u32 a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return i5100_nrecmema_merr(a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static inline u32 i5100_recmema_bank(u32 a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return i5100_nrecmema_bank(a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static inline u32 i5100_recmema_rank(u32 a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return i5100_nrecmema_rank(a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static inline u32 i5100_recmemb_cas(u32 a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return i5100_nrecmemb_cas(a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static inline u32 i5100_recmemb_ras(u32 a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return i5100_nrecmemb_ras(a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* some generic limits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define I5100_MAX_RANKS_PER_CHAN 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define I5100_CHANNELS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define I5100_MAX_RANKS_PER_DIMM 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define I5100_DIMM_ADDR_LINES (6 - 3) /* 64 bits / 8 bits per byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define I5100_MAX_DIMM_SLOTS_PER_CHAN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define I5100_MAX_RANK_INTERLEAVE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define I5100_MAX_DMIRS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define I5100_SCRUB_REFRESH_RATE (5 * 60 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct i5100_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* ranks on each dimm -- 0 maps to not present -- obtained via SPD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) int dimm_numrank[I5100_CHANNELS][I5100_MAX_DIMM_SLOTS_PER_CHAN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * mainboard chip select map -- maps i5100 chip selects to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * DIMM slot chip selects. In the case of only 4 ranks per
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * channel, the mapping is fairly obvious but not unique.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * we map -1 -> NC and assume both channels use the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * map...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int dimm_csmap[I5100_MAX_DIMM_SLOTS_PER_CHAN][I5100_MAX_RANKS_PER_DIMM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* memory interleave range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) u64 limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) unsigned way[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) } mir[I5100_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* adjusted memory interleave range register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) unsigned amir[I5100_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* dimm interleave range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) unsigned rank[I5100_MAX_RANK_INTERLEAVE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u64 limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) } dmir[I5100_CHANNELS][I5100_MAX_DMIRS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* memory technology registers... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) unsigned present; /* 0 or 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) unsigned ethrottle; /* 0 or 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) unsigned width; /* 4 or 8 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) unsigned numbank; /* 2 or 3 lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) unsigned numrow; /* 13 .. 16 lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) unsigned numcol; /* 11 .. 12 lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) } mtr[I5100_CHANNELS][I5100_MAX_RANKS_PER_CHAN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u64 tolm; /* top of low memory in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) unsigned ranksperchan; /* number of ranks per channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct pci_dev *mc; /* device 16 func 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct pci_dev *einj; /* device 19 func 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct pci_dev *ch0mm; /* device 21 func 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct pci_dev *ch1mm; /* device 22 func 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct delayed_work i5100_scrubbing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) int scrub_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* Error injection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) u8 inject_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) u8 inject_hlinesel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u8 inject_deviceptr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u8 inject_deviceptr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u16 inject_eccmask1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) u16 inject_eccmask2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct dentry *debugfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static struct dentry *i5100_debugfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* map a rank/chan to a slot number on the mainboard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static int i5100_rank_to_slot(const struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) int chan, int rank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) const struct i5100_priv *priv = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CHAN; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) const int numrank = priv->dimm_numrank[chan][i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) for (j = 0; j < numrank; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (priv->dimm_csmap[i][j] == rank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return i * 2 + chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static const char *i5100_err_msg(unsigned err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static const char *merrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) "unknown", /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) "uncorrectable data ECC on replay", /* 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) "unknown", /* 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) "unknown", /* 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) "aliased uncorrectable demand data ECC", /* 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) "aliased uncorrectable spare-copy data ECC", /* 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) "aliased uncorrectable patrol data ECC", /* 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) "unknown", /* 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) "unknown", /* 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) "unknown", /* 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) "non-aliased uncorrectable demand data ECC", /* 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) "non-aliased uncorrectable spare-copy data ECC", /* 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) "non-aliased uncorrectable patrol data ECC", /* 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) "unknown", /* 13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) "correctable demand data ECC", /* 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) "correctable spare-copy data ECC", /* 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) "correctable patrol data ECC", /* 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) "unknown", /* 17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) "SPD protocol error", /* 18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) "unknown", /* 19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) "spare copy initiated", /* 20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) "spare copy completed", /* 21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) unsigned i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) for (i = 0; i < ARRAY_SIZE(merrs); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (1 << i & err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return merrs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return "none";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* convert csrow index into a rank (per channel -- 0..5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static unsigned int i5100_csrow_to_rank(const struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) unsigned int csrow)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) const struct i5100_priv *priv = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return csrow % priv->ranksperchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* convert csrow index into a channel (0..1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static unsigned int i5100_csrow_to_chan(const struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) unsigned int csrow)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) const struct i5100_priv *priv = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return csrow / priv->ranksperchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static void i5100_handle_ce(struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) int chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) unsigned bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) unsigned rank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) unsigned long syndrome,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) unsigned cas,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) unsigned ras,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) const char *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) char detail[80];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* Form out message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) snprintf(detail, sizeof(detail),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) "bank %u, cas %u, ras %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) bank, cas, ras);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 0, 0, syndrome,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) chan, rank, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) msg, detail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static void i5100_handle_ue(struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) int chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) unsigned bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) unsigned rank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) unsigned long syndrome,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) unsigned cas,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) unsigned ras,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) const char *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) char detail[80];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* Form out message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) snprintf(detail, sizeof(detail),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) "bank %u, cas %u, ras %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) bank, cas, ras);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 0, 0, syndrome,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) chan, rank, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) msg, detail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static void i5100_read_log(struct mem_ctl_info *mci, int chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) u32 ferr, u32 nerr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) struct i5100_priv *priv = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct pci_dev *pdev = (chan) ? priv->ch1mm : priv->ch0mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) u32 dw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) u32 dw2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) unsigned syndrome = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) unsigned merr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) unsigned bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) unsigned rank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) unsigned cas;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) unsigned ras;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) pci_read_config_dword(pdev, I5100_VALIDLOG, &dw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (i5100_validlog_redmemvalid(dw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) pci_read_config_dword(pdev, I5100_REDMEMA, &dw2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) syndrome = dw2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) pci_read_config_dword(pdev, I5100_REDMEMB, &dw2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (i5100_validlog_recmemvalid(dw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) const char *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) pci_read_config_dword(pdev, I5100_RECMEMA, &dw2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) merr = i5100_recmema_merr(dw2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) bank = i5100_recmema_bank(dw2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) rank = i5100_recmema_rank(dw2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) pci_read_config_dword(pdev, I5100_RECMEMB, &dw2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) cas = i5100_recmemb_cas(dw2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) ras = i5100_recmemb_ras(dw2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* FIXME: not really sure if this is what merr is...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (!merr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) msg = i5100_err_msg(ferr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) msg = i5100_err_msg(nerr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) i5100_handle_ce(mci, chan, bank, rank, syndrome, cas, ras, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (i5100_validlog_nrecmemvalid(dw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) const char *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) pci_read_config_dword(pdev, I5100_NRECMEMA, &dw2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) merr = i5100_nrecmema_merr(dw2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) bank = i5100_nrecmema_bank(dw2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) rank = i5100_nrecmema_rank(dw2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) pci_read_config_dword(pdev, I5100_NRECMEMB, &dw2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) cas = i5100_nrecmemb_cas(dw2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) ras = i5100_nrecmemb_ras(dw2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* FIXME: not really sure if this is what merr is...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (!merr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) msg = i5100_err_msg(ferr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) msg = i5100_err_msg(nerr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) i5100_handle_ue(mci, chan, bank, rank, syndrome, cas, ras, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) pci_write_config_dword(pdev, I5100_VALIDLOG, dw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static void i5100_check_error(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct i5100_priv *priv = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) u32 dw, dw2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) pci_read_config_dword(priv->mc, I5100_FERR_NF_MEM, &dw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (i5100_ferr_nf_mem_any(dw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) pci_read_config_dword(priv->mc, I5100_NERR_NF_MEM, &dw2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) i5100_read_log(mci, i5100_ferr_nf_mem_chan_indx(dw),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) i5100_ferr_nf_mem_any(dw),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) i5100_nerr_nf_mem_any(dw2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) pci_write_config_dword(priv->mc, I5100_NERR_NF_MEM, dw2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) pci_write_config_dword(priv->mc, I5100_FERR_NF_MEM, dw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* The i5100 chipset will scrub the entire memory once, then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * set a done bit. Continuous scrubbing is achieved by enqueing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * delayed work to a workqueue, checking every few minutes if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * the scrubbing has completed and if so reinitiating it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static void i5100_refresh_scrubbing(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct delayed_work *i5100_scrubbing = to_delayed_work(work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct i5100_priv *priv = container_of(i5100_scrubbing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) struct i5100_priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) i5100_scrubbing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) u32 dw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) pci_read_config_dword(priv->mc, I5100_MC, &dw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (priv->scrub_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) pci_read_config_dword(priv->mc, I5100_MC, &dw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (i5100_mc_scrbdone(dw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) dw |= I5100_MC_SCRBEN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) pci_write_config_dword(priv->mc, I5100_MC, dw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) pci_read_config_dword(priv->mc, I5100_MC, &dw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) schedule_delayed_work(&(priv->i5100_scrubbing),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) I5100_SCRUB_REFRESH_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * The bandwidth is based on experimentation, feel free to refine it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static int i5100_set_scrub_rate(struct mem_ctl_info *mci, u32 bandwidth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct i5100_priv *priv = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) u32 dw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) pci_read_config_dword(priv->mc, I5100_MC, &dw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (bandwidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) priv->scrub_enable = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) dw |= I5100_MC_SCRBEN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) schedule_delayed_work(&(priv->i5100_scrubbing),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) I5100_SCRUB_REFRESH_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) priv->scrub_enable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) dw &= ~I5100_MC_SCRBEN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) cancel_delayed_work(&(priv->i5100_scrubbing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) pci_write_config_dword(priv->mc, I5100_MC, dw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) pci_read_config_dword(priv->mc, I5100_MC, &dw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) bandwidth = 5900000 * i5100_mc_scrben(dw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) return bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static int i5100_get_scrub_rate(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct i5100_priv *priv = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) u32 dw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) pci_read_config_dword(priv->mc, I5100_MC, &dw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return 5900000 * i5100_mc_scrben(dw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static struct pci_dev *pci_get_device_func(unsigned vendor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) unsigned device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) unsigned func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) struct pci_dev *ret = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) ret = pci_get_device(vendor, device, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (PCI_FUNC(ret->devfn) == func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static unsigned long i5100_npages(struct mem_ctl_info *mci, unsigned int csrow)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) struct i5100_priv *priv = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) const unsigned int chan_rank = i5100_csrow_to_rank(mci, csrow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) const unsigned int chan = i5100_csrow_to_chan(mci, csrow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) unsigned addr_lines;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /* dimm present? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (!priv->mtr[chan][chan_rank].present)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return 0ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) addr_lines =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) I5100_DIMM_ADDR_LINES +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) priv->mtr[chan][chan_rank].numcol +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) priv->mtr[chan][chan_rank].numrow +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) priv->mtr[chan][chan_rank].numbank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return (unsigned long)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) ((unsigned long long) (1ULL << addr_lines) / PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static void i5100_init_mtr(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) struct i5100_priv *priv = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) struct pci_dev *mms[2] = { priv->ch0mm, priv->ch1mm };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) for (i = 0; i < I5100_CHANNELS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) struct pci_dev *pdev = mms[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) for (j = 0; j < I5100_MAX_RANKS_PER_CHAN; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) const unsigned addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) (j < 4) ? I5100_MTR_0 + j * 2 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) I5100_MTR_4 + (j - 4) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) u16 w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) pci_read_config_word(pdev, addr, &w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) priv->mtr[i][j].present = i5100_mtr_present(w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) priv->mtr[i][j].ethrottle = i5100_mtr_ethrottle(w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) priv->mtr[i][j].width = 4 + 4 * i5100_mtr_width(w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) priv->mtr[i][j].numbank = 2 + i5100_mtr_numbank(w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) priv->mtr[i][j].numrow = 13 + i5100_mtr_numrow(w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) priv->mtr[i][j].numcol = 10 + i5100_mtr_numcol(w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) * FIXME: make this into a real i2c adapter (so that dimm-decode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) * will work)?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static int i5100_read_spd_byte(const struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) u8 ch, u8 slot, u8 addr, u8 *byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct i5100_priv *priv = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) u16 w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) pci_read_config_word(priv->mc, I5100_SPDDATA, &w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (i5100_spddata_busy(w))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) pci_write_config_dword(priv->mc, I5100_SPDCMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) i5100_spdcmd_create(0xa, 1, ch * 4 + slot, addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) 0, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) /* wait up to 100ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) pci_read_config_word(priv->mc, I5100_SPDDATA, &w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (!i5100_spddata_busy(w))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (!i5100_spddata_rdo(w) || i5100_spddata_sbe(w))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) *byte = i5100_spddata_data(w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) * fill dimm chip select map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) * FIXME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) * o not the only way to may chip selects to dimm slots
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) * o investigate if there is some way to obtain this map from the bios
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) static void i5100_init_dimm_csmap(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) struct i5100_priv *priv = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CHAN; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) for (j = 0; j < I5100_MAX_RANKS_PER_DIMM; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) priv->dimm_csmap[i][j] = -1; /* default NC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /* only 2 chip selects per slot... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (priv->ranksperchan == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) priv->dimm_csmap[0][0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) priv->dimm_csmap[0][1] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) priv->dimm_csmap[1][0] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) priv->dimm_csmap[1][1] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) priv->dimm_csmap[2][0] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) priv->dimm_csmap[3][0] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) priv->dimm_csmap[0][0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) priv->dimm_csmap[0][1] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) priv->dimm_csmap[1][0] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) priv->dimm_csmap[1][1] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) priv->dimm_csmap[2][0] = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) priv->dimm_csmap[2][1] = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static void i5100_init_dimm_layout(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) struct i5100_priv *priv = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) for (i = 0; i < I5100_CHANNELS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) for (j = 0; j < I5100_MAX_DIMM_SLOTS_PER_CHAN; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) u8 rank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (i5100_read_spd_byte(mci, i, j, 5, &rank) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) priv->dimm_numrank[i][j] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) priv->dimm_numrank[i][j] = (rank & 3) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) i5100_init_dimm_csmap(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static void i5100_init_interleaving(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) u16 w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) u32 dw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct i5100_priv *priv = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) struct pci_dev *mms[2] = { priv->ch0mm, priv->ch1mm };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) pci_read_config_word(pdev, I5100_TOLM, &w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) priv->tolm = (u64) i5100_tolm_tolm(w) * 256 * 1024 * 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) pci_read_config_word(pdev, I5100_MIR0, &w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) priv->mir[0].limit = (u64) i5100_mir_limit(w) << 28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) priv->mir[0].way[1] = i5100_mir_way1(w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) priv->mir[0].way[0] = i5100_mir_way0(w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) pci_read_config_word(pdev, I5100_MIR1, &w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) priv->mir[1].limit = (u64) i5100_mir_limit(w) << 28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) priv->mir[1].way[1] = i5100_mir_way1(w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) priv->mir[1].way[0] = i5100_mir_way0(w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) pci_read_config_word(pdev, I5100_AMIR_0, &w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) priv->amir[0] = w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) pci_read_config_word(pdev, I5100_AMIR_1, &w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) priv->amir[1] = w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) for (i = 0; i < I5100_CHANNELS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) for (j = 0; j < 5; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) pci_read_config_dword(mms[i], I5100_DMIR + j * 4, &dw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) priv->dmir[i][j].limit =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) (u64) i5100_dmir_limit(dw) << 28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) for (k = 0; k < I5100_MAX_RANKS_PER_DIMM; k++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) priv->dmir[i][j].rank[k] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) i5100_dmir_rank(dw, k);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) i5100_init_mtr(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) static void i5100_init_csrows(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) struct i5100_priv *priv = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) struct dimm_info *dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) mci_for_each_dimm(mci, dimm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) const unsigned long npages = i5100_npages(mci, dimm->idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) const unsigned int chan = i5100_csrow_to_chan(mci, dimm->idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) const unsigned int rank = i5100_csrow_to_rank(mci, dimm->idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) if (!npages)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) dimm->nr_pages = npages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) dimm->grain = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) dimm->dtype = (priv->mtr[chan][rank].width == 4) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) DEV_X4 : DEV_X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) dimm->mtype = MEM_RDDR2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) dimm->edac_mode = EDAC_SECDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) snprintf(dimm->label, sizeof(dimm->label), "DIMM%u",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) i5100_rank_to_slot(mci, chan, rank));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) edac_dbg(2, "dimm channel %d, rank %d, size %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) chan, rank, (long)PAGES_TO_MiB(npages));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) * Error injection routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) static void i5100_do_inject(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) struct i5100_priv *priv = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) u32 mask0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) u16 mask1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) /* MEM[1:0]EINJMSK0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) * 31 - ADDRMATCHEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) * 29:28 - HLINESEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) * 00 Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) * 01 Lower half of cache line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) * 10 Upper half of cache line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) * 11 Both upper and lower parts of cache line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) * 27 - EINJEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) * 25:19 - XORMASK1 for deviceptr1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) * 9:5 - SEC2RAM for deviceptr2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) * 4:0 - FIR2RAM for deviceptr1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) mask0 = ((priv->inject_hlinesel & 0x3) << 28) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) I5100_MEMXEINJMSK0_EINJEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) ((priv->inject_eccmask1 & 0xffff) << 10) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) ((priv->inject_deviceptr2 & 0x1f) << 5) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) (priv->inject_deviceptr1 & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) /* MEM[1:0]EINJMSK1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) * 15:0 - XORMASK2 for deviceptr2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) mask1 = priv->inject_eccmask2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) if (priv->inject_channel == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) pci_write_config_dword(priv->mc, I5100_MEM0EINJMSK0, mask0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) pci_write_config_word(priv->mc, I5100_MEM0EINJMSK1, mask1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) pci_write_config_dword(priv->mc, I5100_MEM1EINJMSK0, mask0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) pci_write_config_word(priv->mc, I5100_MEM1EINJMSK1, mask1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) /* Error Injection Response Function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) * Intel 5100 Memory Controller Hub Chipset (318378) datasheet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) * hints about this register but carry no data about them. All
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) * data regarding device 19 is based on experimentation and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) * Intel 7300 Chipset Memory Controller Hub (318082) datasheet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) * which appears to be accurate for the i5100 in this area.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) * The injection code don't work without setting this register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) * The register needs to be flipped off then on else the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) * will only preform the first injection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) * Stop condition bits 7:4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) * 1010 - Stop after one injection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) * 1011 - Never stop injecting faults
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) * Start condition bits 3:0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) * 1010 - Never start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) * 1011 - Start immediately
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) pci_write_config_byte(priv->einj, I5100_DINJ0, 0xaa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) pci_write_config_byte(priv->einj, I5100_DINJ0, 0xab);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) #define to_mci(k) container_of(k, struct mem_ctl_info, dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) static ssize_t inject_enable_write(struct file *file, const char __user *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) size_t count, loff_t *ppos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) struct device *dev = file->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) struct mem_ctl_info *mci = to_mci(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) i5100_do_inject(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static const struct file_operations i5100_inject_enable_fops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .open = simple_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .write = inject_enable_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .llseek = generic_file_llseek,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) static int i5100_setup_debugfs(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) struct i5100_priv *priv = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (!i5100_debugfs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) priv->debugfs = edac_debugfs_create_dir_at(mci->bus->name, i5100_debugfs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if (!priv->debugfs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) edac_debugfs_create_x8("inject_channel", S_IRUGO | S_IWUSR, priv->debugfs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) &priv->inject_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) edac_debugfs_create_x8("inject_hlinesel", S_IRUGO | S_IWUSR, priv->debugfs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) &priv->inject_hlinesel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) edac_debugfs_create_x8("inject_deviceptr1", S_IRUGO | S_IWUSR, priv->debugfs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) &priv->inject_deviceptr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) edac_debugfs_create_x8("inject_deviceptr2", S_IRUGO | S_IWUSR, priv->debugfs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) &priv->inject_deviceptr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) edac_debugfs_create_x16("inject_eccmask1", S_IRUGO | S_IWUSR, priv->debugfs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) &priv->inject_eccmask1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) edac_debugfs_create_x16("inject_eccmask2", S_IRUGO | S_IWUSR, priv->debugfs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) &priv->inject_eccmask2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) edac_debugfs_create_file("inject_enable", S_IWUSR, priv->debugfs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) &mci->dev, &i5100_inject_enable_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) static int i5100_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) struct mem_ctl_info *mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) struct edac_mc_layer layers[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) struct i5100_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) struct pci_dev *ch0mm, *ch1mm, *einj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) u32 dw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) int ranksperch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) if (PCI_FUNC(pdev->devfn) != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) rc = pci_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) ret = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) goto bail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) /* ECC enabled? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) pci_read_config_dword(pdev, I5100_MC, &dw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) if (!i5100_mc_errdeten(dw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) printk(KERN_INFO "i5100_edac: ECC not enabled.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) goto bail_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) /* figure out how many ranks, from strapped state of 48GB_Mode input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) pci_read_config_dword(pdev, I5100_MS, &dw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) ranksperch = !!(dw & (1 << 8)) * 2 + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) /* enable error reporting... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) pci_read_config_dword(pdev, I5100_EMASK_MEM, &dw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) dw &= ~I5100_FERR_NF_MEM_ANY_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) pci_write_config_dword(pdev, I5100_EMASK_MEM, dw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) /* device 21, func 0, Channel 0 Memory Map, Error Flag/Mask, etc... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) ch0mm = pci_get_device_func(PCI_VENDOR_ID_INTEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) PCI_DEVICE_ID_INTEL_5100_21, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) if (!ch0mm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) goto bail_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) rc = pci_enable_device(ch0mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) ret = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) goto bail_ch0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) /* device 22, func 0, Channel 1 Memory Map, Error Flag/Mask, etc... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) ch1mm = pci_get_device_func(PCI_VENDOR_ID_INTEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) PCI_DEVICE_ID_INTEL_5100_22, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) if (!ch1mm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) goto bail_disable_ch0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) rc = pci_enable_device(ch1mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) ret = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) goto bail_ch1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) layers[0].type = EDAC_MC_LAYER_CHANNEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) layers[0].size = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) layers[0].is_virt_csrow = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) layers[1].type = EDAC_MC_LAYER_SLOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) layers[1].size = ranksperch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) layers[1].is_virt_csrow = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) sizeof(*priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) if (!mci) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) goto bail_disable_ch1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) /* device 19, func 0, Error injection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) einj = pci_get_device_func(PCI_VENDOR_ID_INTEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) PCI_DEVICE_ID_INTEL_5100_19, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) if (!einj) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) goto bail_mc_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) rc = pci_enable_device(einj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) ret = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) goto bail_einj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) mci->pdev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) priv = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) priv->ranksperchan = ranksperch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) priv->mc = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) priv->ch0mm = ch0mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) priv->ch1mm = ch1mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) priv->einj = einj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) INIT_DELAYED_WORK(&(priv->i5100_scrubbing), i5100_refresh_scrubbing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) /* If scrubbing was already enabled by the bios, start maintaining it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) pci_read_config_dword(pdev, I5100_MC, &dw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) if (i5100_mc_scrben(dw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) priv->scrub_enable = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) schedule_delayed_work(&(priv->i5100_scrubbing),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) I5100_SCRUB_REFRESH_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) i5100_init_dimm_layout(pdev, mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) i5100_init_interleaving(pdev, mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) mci->mtype_cap = MEM_FLAG_FB_DDR2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) mci->edac_ctl_cap = EDAC_FLAG_SECDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) mci->edac_cap = EDAC_FLAG_SECDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) mci->mod_name = "i5100_edac.c";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) mci->ctl_name = "i5100";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) mci->dev_name = pci_name(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) mci->ctl_page_to_phys = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) mci->edac_check = i5100_check_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) mci->set_sdram_scrub_rate = i5100_set_scrub_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) mci->get_sdram_scrub_rate = i5100_get_scrub_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) priv->inject_channel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) priv->inject_hlinesel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) priv->inject_deviceptr1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) priv->inject_deviceptr2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) priv->inject_eccmask1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) priv->inject_eccmask2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) i5100_init_csrows(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) /* this strange construction seems to be in every driver, dunno why */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) switch (edac_op_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) case EDAC_OPSTATE_POLL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) case EDAC_OPSTATE_NMI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) edac_op_state = EDAC_OPSTATE_POLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) if (edac_mc_add_mc(mci)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) goto bail_scrub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) i5100_setup_debugfs(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) bail_scrub:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) priv->scrub_enable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) cancel_delayed_work_sync(&(priv->i5100_scrubbing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) pci_disable_device(einj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) bail_einj:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) pci_dev_put(einj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) bail_mc_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) bail_disable_ch1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) pci_disable_device(ch1mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) bail_ch1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) pci_dev_put(ch1mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) bail_disable_ch0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) pci_disable_device(ch0mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) bail_ch0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) pci_dev_put(ch0mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) bail_pdev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) bail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) static void i5100_remove_one(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) struct mem_ctl_info *mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) struct i5100_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) mci = edac_mc_del_mc(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) if (!mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) priv = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) edac_debugfs_remove_recursive(priv->debugfs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) priv->scrub_enable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) cancel_delayed_work_sync(&(priv->i5100_scrubbing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) pci_disable_device(priv->ch0mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) pci_disable_device(priv->ch1mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) pci_disable_device(priv->einj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) pci_dev_put(priv->ch0mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) pci_dev_put(priv->ch1mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) pci_dev_put(priv->einj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) static const struct pci_device_id i5100_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) /* Device 16, Function 0, Channel 0 Memory Map, Error Flag/Mask, ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5100_16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) MODULE_DEVICE_TABLE(pci, i5100_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) static struct pci_driver i5100_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) .name = KBUILD_BASENAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) .probe = i5100_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) .remove = i5100_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) .id_table = i5100_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) static int __init i5100_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) int pci_rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) i5100_debugfs = edac_debugfs_create_dir_at("i5100_edac", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) pci_rc = pci_register_driver(&i5100_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) return (pci_rc < 0) ? pci_rc : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) static void __exit i5100_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) edac_debugfs_remove(i5100_debugfs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) pci_unregister_driver(&i5100_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) module_init(i5100_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) module_exit(i5100_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) MODULE_AUTHOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) ("Arthur Jones <ajones@riverbed.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) MODULE_DESCRIPTION("MC Driver for Intel I5100 memory controllers");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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