^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Intel 3200/3210 Memory Controller kernel module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2008-2009 Akamai Technologies, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Portions by Hitoshi Mitake <h.mitake@gmail.com>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file may be distributed under the terms of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * GNU General Public License.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pci_ids.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/edac.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "edac_module.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io-64-nonatomic-lo-hi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define EDAC_MOD_STR "i3200_edac"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PCI_DEVICE_ID_INTEL_3200_HB 0x29f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define I3200_DIMMS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define I3200_RANKS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define I3200_RANKS_PER_CHANNEL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define I3200_CHANNELS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* Intel 3200 register addresses - device 0 function 0 - DRAM Controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define I3200_MCHBAR_LOW 0x48 /* MCH Memory Mapped Register BAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define I3200_MCHBAR_HIGH 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define I3200_MCHBAR_MASK 0xfffffc000ULL /* bits 35:14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define I3200_MMR_WINDOW_SIZE 16384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define I3200_TOM 0xa0 /* Top of Memory (16b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * 15:10 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * 9:0 total populated physical memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define I3200_TOM_MASK 0x3ff /* bits 9:0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define I3200_TOM_SHIFT 26 /* 64MiB grain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define I3200_ERRSTS 0xc8 /* Error Status Register (16b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * 15 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * 14 Isochronous TBWRR Run Behind FIFO Full
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * (ITCV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * 13 Isochronous TBWRR Run Behind FIFO Put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * (ITSTV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * 12 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * 11 MCH Thermal Sensor Event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * for SMI/SCI/SERR (GTSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * 10 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * 9 LOCK to non-DRAM Memory Flag (LCKF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * 8 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * 7 DRAM Throttle Flag (DTF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * 6:2 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * 1 Multi-bit DRAM ECC Error Flag (DMERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * 0 Single-bit DRAM ECC Error Flag (DSERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define I3200_ERRSTS_UE 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define I3200_ERRSTS_CE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define I3200_ERRSTS_BITS (I3200_ERRSTS_UE | I3200_ERRSTS_CE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* Intel MMIO register space - device 0 function 0 - MMR space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define I3200_C0DRB 0x200 /* Channel 0 DRAM Rank Boundary (16b x 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * 15:10 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * 9:0 Channel 0 DRAM Rank Boundary Address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define I3200_C1DRB 0x600 /* Channel 1 DRAM Rank Boundary (16b x 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define I3200_DRB_MASK 0x3ff /* bits 9:0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define I3200_DRB_SHIFT 26 /* 64MiB grain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define I3200_C0ECCERRLOG 0x280 /* Channel 0 ECC Error Log (64b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * 63:48 Error Column Address (ERRCOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * 47:32 Error Row Address (ERRROW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * 31:29 Error Bank Address (ERRBANK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * 28:27 Error Rank Address (ERRRANK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * 26:24 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * 23:16 Error Syndrome (ERRSYND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * 15: 2 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * 1 Multiple Bit Error Status (MERRSTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * 0 Correctable Error Status (CERRSTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define I3200_C1ECCERRLOG 0x680 /* Chan 1 ECC Error Log (64b) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define I3200_ECCERRLOG_CE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define I3200_ECCERRLOG_UE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define I3200_ECCERRLOG_RANK_BITS 0x18000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define I3200_ECCERRLOG_RANK_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define I3200_ECCERRLOG_SYNDROME_BITS 0xff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define I3200_ECCERRLOG_SYNDROME_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define I3200_CAPID0 0xe0 /* P.95 of spec for details */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct i3200_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) void __iomem *window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static int nr_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int how_many_channels(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int n_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned char capid0_8b; /* 8th byte of CAPID0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) pci_read_config_byte(pdev, I3200_CAPID0 + 8, &capid0_8b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (capid0_8b & 0x20) { /* check DCD: Dual Channel Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) edac_dbg(0, "In single channel mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) n_channels = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) edac_dbg(0, "In dual channel mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) n_channels = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (capid0_8b & 0x10) /* check if both channels are filled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) edac_dbg(0, "2 DIMMS per channel disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) edac_dbg(0, "2 DIMMS per channel enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return n_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static unsigned long eccerrlog_syndrome(u64 log)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return (log & I3200_ECCERRLOG_SYNDROME_BITS) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) I3200_ECCERRLOG_SYNDROME_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static int eccerrlog_row(int channel, u64 log)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u64 rank = ((log & I3200_ECCERRLOG_RANK_BITS) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) I3200_ECCERRLOG_RANK_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return rank | (channel * I3200_RANKS_PER_CHANNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) enum i3200_chips {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) I3200 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct i3200_dev_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) const char *ctl_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct i3200_error_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u16 errsts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u16 errsts2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u64 eccerrlog[I3200_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static const struct i3200_dev_info i3200_devs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) [I3200] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .ctl_name = "i3200"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static struct pci_dev *mci_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int i3200_registered = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static void i3200_clear_error_info(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) pdev = to_pci_dev(mci->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * Clear any error bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * (Yes, we really clear bits by writing 1 to them.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) pci_write_bits16(pdev, I3200_ERRSTS, I3200_ERRSTS_BITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) I3200_ERRSTS_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static void i3200_get_and_clear_error_info(struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct i3200_error_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct i3200_priv *priv = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) void __iomem *window = priv->window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) pdev = to_pci_dev(mci->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * This is a mess because there is no atomic way to read all the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * registers at once and the registers can transition from CE being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * overwritten by UE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) pci_read_config_word(pdev, I3200_ERRSTS, &info->errsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (!(info->errsts & I3200_ERRSTS_BITS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) info->eccerrlog[0] = readq(window + I3200_C0ECCERRLOG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (nr_channels == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) info->eccerrlog[1] = readq(window + I3200_C1ECCERRLOG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) pci_read_config_word(pdev, I3200_ERRSTS, &info->errsts2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * If the error is the same for both reads then the first set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * of reads is valid. If there is a change then there is a CE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * with no info and the second set of reads is valid and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * should be UE info.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if ((info->errsts ^ info->errsts2) & I3200_ERRSTS_BITS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) info->eccerrlog[0] = readq(window + I3200_C0ECCERRLOG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (nr_channels == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) info->eccerrlog[1] = readq(window + I3200_C1ECCERRLOG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) i3200_clear_error_info(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static void i3200_process_error_info(struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct i3200_error_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) int channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u64 log;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (!(info->errsts & I3200_ERRSTS_BITS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if ((info->errsts ^ info->errsts2) & I3200_ERRSTS_BITS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) -1, -1, -1, "UE overwrote CE", "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) info->errsts = info->errsts2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) for (channel = 0; channel < nr_channels; channel++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) log = info->eccerrlog[channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (log & I3200_ECCERRLOG_UE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) eccerrlog_row(channel, log),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) -1, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) "i3000 UE", "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) } else if (log & I3200_ECCERRLOG_CE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 0, 0, eccerrlog_syndrome(log),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) eccerrlog_row(channel, log),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) -1, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) "i3000 CE", "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static void i3200_check(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct i3200_error_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) edac_dbg(1, "MC%d\n", mci->mc_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) i3200_get_and_clear_error_info(mci, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) i3200_process_error_info(mci, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static void __iomem *i3200_map_mchbar(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) u64 mchbar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u32 mchbar_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u32 mchbar_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) void __iomem *window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) pci_read_config_dword(pdev, I3200_MCHBAR_LOW, &u.mchbar_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) pci_read_config_dword(pdev, I3200_MCHBAR_HIGH, &u.mchbar_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u.mchbar &= I3200_MCHBAR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (u.mchbar != (resource_size_t)u.mchbar) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) printk(KERN_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) "i3200: mmio space beyond accessible range (0x%llx)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) (unsigned long long)u.mchbar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) window = ioremap(u.mchbar, I3200_MMR_WINDOW_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (!window)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) printk(KERN_ERR "i3200: cannot map mmio space at 0x%llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) (unsigned long long)u.mchbar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static void i3200_get_drbs(void __iomem *window,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) for (i = 0; i < I3200_RANKS_PER_CHANNEL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) drbs[0][i] = readw(window + I3200_C0DRB + 2*i) & I3200_DRB_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) drbs[1][i] = readw(window + I3200_C1DRB + 2*i) & I3200_DRB_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) edac_dbg(0, "drb[0][%d] = %d, drb[1][%d] = %d\n", i, drbs[0][i], i, drbs[1][i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static bool i3200_is_stacked(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u16 tom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) pci_read_config_word(pdev, I3200_TOM, &tom);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) tom &= I3200_TOM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return drbs[I3200_CHANNELS - 1][I3200_RANKS_PER_CHANNEL - 1] == tom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static unsigned long drb_to_nr_pages(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL], bool stacked,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) int channel, int rank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) int n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) n = drbs[channel][rank];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (!n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (rank > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) n -= drbs[channel][rank - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (stacked && (channel == 1) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) drbs[channel][rank] == drbs[channel][I3200_RANKS_PER_CHANNEL - 1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) n -= drbs[0][I3200_RANKS_PER_CHANNEL - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) n <<= (I3200_DRB_SHIFT - PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int i3200_probe1(struct pci_dev *pdev, int dev_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct mem_ctl_info *mci = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct edac_mc_layer layers[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) bool stacked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) void __iomem *window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct i3200_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) edac_dbg(0, "MC:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) window = i3200_map_mchbar(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (!window)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) i3200_get_drbs(window, drbs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) nr_channels = how_many_channels(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) layers[0].size = I3200_DIMMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) layers[0].is_virt_csrow = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) layers[1].type = EDAC_MC_LAYER_CHANNEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) layers[1].size = nr_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) layers[1].is_virt_csrow = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) sizeof(struct i3200_priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (!mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) edac_dbg(3, "MC: init mci\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) mci->pdev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) mci->mtype_cap = MEM_FLAG_DDR2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) mci->edac_ctl_cap = EDAC_FLAG_SECDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) mci->edac_cap = EDAC_FLAG_SECDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) mci->mod_name = EDAC_MOD_STR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) mci->ctl_name = i3200_devs[dev_idx].ctl_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) mci->dev_name = pci_name(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) mci->edac_check = i3200_check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) mci->ctl_page_to_phys = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) priv = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) priv->window = window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) stacked = i3200_is_stacked(pdev, drbs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * The dram rank boundary (DRB) reg values are boundary addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * for each DRAM rank with a granularity of 64MB. DRB regs are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * cumulative; the last one will contain the total memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * contained in all ranks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) for (i = 0; i < I3200_DIMMS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) unsigned long nr_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) for (j = 0; j < nr_channels; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct dimm_info *dimm = edac_get_dimm(mci, i, j, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) nr_pages = drb_to_nr_pages(drbs, stacked, j, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (nr_pages == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) edac_dbg(0, "csrow %d, channel %d%s, size = %ld MiB\n", i, j,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) stacked ? " (stacked)" : "", PAGES_TO_MiB(nr_pages));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) dimm->nr_pages = nr_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) dimm->grain = nr_pages << PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) dimm->mtype = MEM_DDR2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) dimm->dtype = DEV_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) dimm->edac_mode = EDAC_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) i3200_clear_error_info(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (edac_mc_add_mc(mci)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) edac_dbg(3, "MC: failed edac_mc_add_mc()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* get this far and it's successful */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) edac_dbg(3, "MC: success\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) iounmap(window);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static int i3200_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) edac_dbg(0, "MC:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (pci_enable_device(pdev) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) rc = i3200_probe1(pdev, ent->driver_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (!mci_pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) mci_pdev = pci_dev_get(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static void i3200_remove_one(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct mem_ctl_info *mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct i3200_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) edac_dbg(0, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) mci = edac_mc_del_mc(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (!mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) priv = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) iounmap(priv->window);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static const struct pci_device_id i3200_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) PCI_VEND_DEV(INTEL, 3200_HB), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) I3200},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) } /* 0 terminated list. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) MODULE_DEVICE_TABLE(pci, i3200_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static struct pci_driver i3200_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .name = EDAC_MOD_STR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .probe = i3200_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .remove = i3200_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .id_table = i3200_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static int __init i3200_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) int pci_rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) edac_dbg(3, "MC:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* Ensure that the OPSTATE is set correctly for POLL or NMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) opstate_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) pci_rc = pci_register_driver(&i3200_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (pci_rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) goto fail0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (!mci_pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) i3200_registered = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) PCI_DEVICE_ID_INTEL_3200_HB, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (!mci_pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) edac_dbg(0, "i3200 pci_get_device fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) pci_rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) goto fail1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) pci_rc = i3200_init_one(mci_pdev, i3200_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (pci_rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) edac_dbg(0, "i3200 init fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) pci_rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) goto fail1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) fail1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) pci_unregister_driver(&i3200_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) fail0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) pci_dev_put(mci_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return pci_rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static void __exit i3200_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) edac_dbg(3, "MC:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) pci_unregister_driver(&i3200_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (!i3200_registered) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) i3200_remove_one(mci_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) pci_dev_put(mci_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) module_init(i3200_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) module_exit(i3200_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) MODULE_AUTHOR("Akamai Technologies, Inc.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) MODULE_DESCRIPTION("MC support for Intel 3200 memory hub controllers");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) module_param(edac_op_state, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags