^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Intel 3000/3010 Memory Controller kernel module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2007 Akamai Technologies, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Shamelessly copied from:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Intel D82875P Memory Controller kernel module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * (C) 2003 Linux Networx (http://lnxi.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This file may be distributed under the terms of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * GNU General Public License.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pci_ids.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/edac.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "edac_module.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define EDAC_MOD_STR "i3000_edac"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define I3000_RANKS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define I3000_RANKS_PER_CHANNEL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define I3000_CHANNELS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Intel 3000 register addresses - device 0 function 0 - DRAM Controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define I3000_MCHBAR 0x44 /* MCH Memory Mapped Register BAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define I3000_MCHBAR_MASK 0xffffc000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define I3000_MMR_WINDOW_SIZE 16384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define I3000_EDEAP 0x70 /* Extended DRAM Error Address Pointer (8b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * 7:1 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * 0 bit 32 of address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define I3000_DEAP 0x58 /* DRAM Error Address Pointer (32b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * 31:7 address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * 6:1 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * 0 Error channel 0/1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define I3000_DEAP_GRAIN (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Helper functions to decode the DEAP/EDEAP hardware registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * The type promotion here is deliberate; we're deriving an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * unsigned long pfn and offset from hardware regs which are u8/u32.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static inline unsigned long deap_pfn(u8 edeap, u32 deap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) deap >>= PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) deap |= (edeap & 1) << (32 - PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return deap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static inline unsigned long deap_offset(u32 deap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return deap & ~(I3000_DEAP_GRAIN - 1) & ~PAGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static inline int deap_channel(u32 deap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return deap & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define I3000_DERRSYN 0x5c /* DRAM Error Syndrome (8b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * 7:0 DRAM ECC Syndrome
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define I3000_ERRSTS 0xc8 /* Error Status Register (16b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * 15:12 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * 11 MCH Thermal Sensor Event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * for SMI/SCI/SERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * 10 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * 9 LOCK to non-DRAM Memory Flag (LCKF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * 8 Received Refresh Timeout Flag (RRTOF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * 7:2 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * 1 Multi-bit DRAM ECC Error Flag (DMERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * 0 Single-bit DRAM ECC Error Flag (DSERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define I3000_ERRSTS_BITS 0x0b03 /* bits which indicate errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define I3000_ERRSTS_UE 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define I3000_ERRSTS_CE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define I3000_ERRCMD 0xca /* Error Command (16b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * 15:12 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * 11 SERR on MCH Thermal Sensor Event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * (TSESERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * 10 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * 9 SERR on LOCK to non-DRAM Memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * (LCKERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * 8 SERR on DRAM Refresh Timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * (DRTOERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * 7:2 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * 1 SERR Multi-Bit DRAM ECC Error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * (DMERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * 0 SERR on Single-Bit ECC Error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * (DSERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Intel MMIO register space - device 0 function 0 - MMR space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define I3000_DRB_SHIFT 25 /* 32MiB grain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define I3000_C0DRB 0x100 /* Channel 0 DRAM Rank Boundary (8b x 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * 7:0 Channel 0 DRAM Rank Boundary Address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define I3000_C1DRB 0x180 /* Channel 1 DRAM Rank Boundary (8b x 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * 7:0 Channel 1 DRAM Rank Boundary Address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define I3000_C0DRA 0x108 /* Channel 0 DRAM Rank Attribute (8b x 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * 7 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * 6:4 DRAM odd Rank Attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * 3 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * 2:0 DRAM even Rank Attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * Each attribute defines the page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * size of the corresponding rank:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * 000: unpopulated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * 001: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * 010: 4 KB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * 011: 8 KB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * 100: 16 KB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * Others: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define I3000_C1DRA 0x188 /* Channel 1 DRAM Rank Attribute (8b x 2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static inline unsigned char odd_rank_attrib(unsigned char dra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return (dra & 0x70) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static inline unsigned char even_rank_attrib(unsigned char dra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return dra & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define I3000_C0DRC0 0x120 /* DRAM Controller Mode 0 (32b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * 31:30 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * 29 Initialization Complete (IC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * 28:11 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * 10:8 Refresh Mode Select (RMS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * 7 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * 6:4 Mode Select (SMS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * 3:2 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * 1:0 DRAM Type (DT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define I3000_C0DRC1 0x124 /* DRAM Controller Mode 1 (32b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * 31 Enhanced Addressing Enable (ENHADE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * 30:0 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) enum i3000p_chips {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) I3000 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct i3000_dev_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) const char *ctl_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct i3000_error_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u16 errsts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u8 derrsyn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u8 edeap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u32 deap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u16 errsts2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static const struct i3000_dev_info i3000_devs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) [I3000] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .ctl_name = "i3000"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static struct pci_dev *mci_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static int i3000_registered = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static struct edac_pci_ctl_info *i3000_pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static void i3000_get_error_info(struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct i3000_error_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) pdev = to_pci_dev(mci->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * This is a mess because there is no atomic way to read all the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * registers at once and the registers can transition from CE being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * overwritten by UE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) pci_read_config_word(pdev, I3000_ERRSTS, &info->errsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (!(info->errsts & I3000_ERRSTS_BITS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) pci_read_config_byte(pdev, I3000_EDEAP, &info->edeap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) pci_read_config_dword(pdev, I3000_DEAP, &info->deap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) pci_read_config_byte(pdev, I3000_DERRSYN, &info->derrsyn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) pci_read_config_word(pdev, I3000_ERRSTS, &info->errsts2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * If the error is the same for both reads then the first set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * of reads is valid. If there is a change then there is a CE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * with no info and the second set of reads is valid and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * should be UE info.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if ((info->errsts ^ info->errsts2) & I3000_ERRSTS_BITS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) pci_read_config_byte(pdev, I3000_EDEAP, &info->edeap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) pci_read_config_dword(pdev, I3000_DEAP, &info->deap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) pci_read_config_byte(pdev, I3000_DERRSYN, &info->derrsyn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * Clear any error bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * (Yes, we really clear bits by writing 1 to them.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) pci_write_bits16(pdev, I3000_ERRSTS, I3000_ERRSTS_BITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) I3000_ERRSTS_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static int i3000_process_error_info(struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct i3000_error_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int handle_errors)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int row, multi_chan, channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) unsigned long pfn, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) multi_chan = mci->csrows[0]->nr_channels - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (!(info->errsts & I3000_ERRSTS_BITS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (!handle_errors)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if ((info->errsts ^ info->errsts2) & I3000_ERRSTS_BITS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) -1, -1, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) "UE overwrote CE", "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) info->errsts = info->errsts2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) pfn = deap_pfn(info->edeap, info->deap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) offset = deap_offset(info->deap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) channel = deap_channel(info->deap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) row = edac_mc_find_csrow_by_page(mci, pfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (info->errsts & I3000_ERRSTS_UE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) pfn, offset, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) row, -1, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) "i3000 UE", "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) pfn, offset, info->derrsyn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) row, multi_chan ? channel : 0, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) "i3000 CE", "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static void i3000_check(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct i3000_error_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) edac_dbg(1, "MC%d\n", mci->mc_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) i3000_get_error_info(mci, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) i3000_process_error_info(mci, &info, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static int i3000_is_interleaved(const unsigned char *c0dra,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) const unsigned char *c1dra,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) const unsigned char *c0drb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) const unsigned char *c1drb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * If the channels aren't populated identically then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * we're not interleaved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) for (i = 0; i < I3000_RANKS_PER_CHANNEL / 2; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (odd_rank_attrib(c0dra[i]) != odd_rank_attrib(c1dra[i]) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) even_rank_attrib(c0dra[i]) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) even_rank_attrib(c1dra[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * If the rank boundaries for the two channels are different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * then we're not interleaved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) for (i = 0; i < I3000_RANKS_PER_CHANNEL; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (c0drb[i] != c1drb[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static int i3000_probe1(struct pci_dev *pdev, int dev_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct mem_ctl_info *mci = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct edac_mc_layer layers[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) unsigned long last_cumul_size, nr_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) int interleaved, nr_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) unsigned char dra[I3000_RANKS / 2], drb[I3000_RANKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) unsigned char *c0dra = dra, *c1dra = &dra[I3000_RANKS_PER_CHANNEL / 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) unsigned char *c0drb = drb, *c1drb = &drb[I3000_RANKS_PER_CHANNEL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) unsigned long mchbar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) void __iomem *window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) edac_dbg(0, "MC:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) pci_read_config_dword(pdev, I3000_MCHBAR, (u32 *) & mchbar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) mchbar &= I3000_MCHBAR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) window = ioremap(mchbar, I3000_MMR_WINDOW_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (!window) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) printk(KERN_ERR "i3000: cannot map mmio space at 0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) mchbar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) c0dra[0] = readb(window + I3000_C0DRA + 0); /* ranks 0,1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) c0dra[1] = readb(window + I3000_C0DRA + 1); /* ranks 2,3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) c1dra[0] = readb(window + I3000_C1DRA + 0); /* ranks 0,1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) c1dra[1] = readb(window + I3000_C1DRA + 1); /* ranks 2,3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) for (i = 0; i < I3000_RANKS_PER_CHANNEL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) c0drb[i] = readb(window + I3000_C0DRB + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) c1drb[i] = readb(window + I3000_C1DRB + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) iounmap(window);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * Figure out how many channels we have.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * If we have what the datasheet calls "asymmetric channels"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * (essentially the same as what was called "virtual single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * channel mode" in the i82875) then it's a single channel as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * far as EDAC is concerned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) interleaved = i3000_is_interleaved(c0dra, c1dra, c0drb, c1drb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) nr_channels = interleaved ? 2 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) layers[0].size = I3000_RANKS / nr_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) layers[0].is_virt_csrow = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) layers[1].type = EDAC_MC_LAYER_CHANNEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) layers[1].size = nr_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) layers[1].is_virt_csrow = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (!mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) edac_dbg(3, "MC: init mci\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) mci->pdev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) mci->mtype_cap = MEM_FLAG_DDR2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) mci->edac_ctl_cap = EDAC_FLAG_SECDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) mci->edac_cap = EDAC_FLAG_SECDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) mci->mod_name = EDAC_MOD_STR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) mci->ctl_name = i3000_devs[dev_idx].ctl_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) mci->dev_name = pci_name(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) mci->edac_check = i3000_check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) mci->ctl_page_to_phys = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * The dram rank boundary (DRB) reg values are boundary addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * for each DRAM rank with a granularity of 32MB. DRB regs are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * cumulative; the last one will contain the total memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * contained in all ranks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * If we're in interleaved mode then we're only walking through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * the ranks of controller 0, so we double all the values we see.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) for (last_cumul_size = i = 0; i < mci->nr_csrows; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) u32 cumul_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct csrow_info *csrow = mci->csrows[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) value = drb[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) cumul_size = value << (I3000_DRB_SHIFT - PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (interleaved)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) cumul_size <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) edac_dbg(3, "MC: (%d) cumul_size 0x%x\n", i, cumul_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (cumul_size == last_cumul_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) csrow->first_page = last_cumul_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) csrow->last_page = cumul_size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) nr_pages = cumul_size - last_cumul_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) last_cumul_size = cumul_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) for (j = 0; j < nr_channels; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct dimm_info *dimm = csrow->channels[j]->dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) dimm->nr_pages = nr_pages / nr_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) dimm->grain = I3000_DEAP_GRAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) dimm->mtype = MEM_DDR2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) dimm->dtype = DEV_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) dimm->edac_mode = EDAC_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * Clear any error bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * (Yes, we really clear bits by writing 1 to them.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) pci_write_bits16(pdev, I3000_ERRSTS, I3000_ERRSTS_BITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) I3000_ERRSTS_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (edac_mc_add_mc(mci)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) edac_dbg(3, "MC: failed edac_mc_add_mc()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* allocating generic PCI control info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) i3000_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (!i3000_pci) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) "%s(): Unable to create PCI control\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) "%s(): PCI error report via EDAC not setup\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* get this far and it's successful */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) edac_dbg(3, "MC: success\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* returns count (>= 0), or negative on error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static int i3000_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) edac_dbg(0, "MC:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (pci_enable_device(pdev) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) rc = i3000_probe1(pdev, ent->driver_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (!mci_pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) mci_pdev = pci_dev_get(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static void i3000_remove_one(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct mem_ctl_info *mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) edac_dbg(0, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (i3000_pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) edac_pci_release_generic_ctl(i3000_pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) mci = edac_mc_del_mc(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (!mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static const struct pci_device_id i3000_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) PCI_VEND_DEV(INTEL, 3000_HB), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) I3000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) } /* 0 terminated list. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) MODULE_DEVICE_TABLE(pci, i3000_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static struct pci_driver i3000_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .name = EDAC_MOD_STR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .probe = i3000_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .remove = i3000_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .id_table = i3000_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static int __init i3000_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) int pci_rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) edac_dbg(3, "MC:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* Ensure that the OPSTATE is set correctly for POLL or NMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) opstate_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) pci_rc = pci_register_driver(&i3000_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (pci_rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) goto fail0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (!mci_pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) i3000_registered = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) PCI_DEVICE_ID_INTEL_3000_HB, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (!mci_pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) edac_dbg(0, "i3000 pci_get_device fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) pci_rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) goto fail1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) pci_rc = i3000_init_one(mci_pdev, i3000_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (pci_rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) edac_dbg(0, "i3000 init fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) pci_rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) goto fail1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) fail1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) pci_unregister_driver(&i3000_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) fail0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) pci_dev_put(mci_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return pci_rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static void __exit i3000_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) edac_dbg(3, "MC:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) pci_unregister_driver(&i3000_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (!i3000_registered) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) i3000_remove_one(mci_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) pci_dev_put(mci_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) module_init(i3000_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) module_exit(i3000_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) MODULE_AUTHOR("Akamai Technologies Arthur Ulfeldt/Jason Uhlenkott");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) MODULE_DESCRIPTION("MC support for Intel 3000 memory hub controllers");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) module_param(edac_op_state, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags