^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Freescale Memory Controller kernel module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Support Power-based SoCs including MPC85xx, MPC86xx, MPC83xx and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * ARM-based Layerscape SoCs including LS2xxx and LS1021A. Originally
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * split out from mpc85xx_edac EDAC driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Dave Jiang <djiang@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * the terms of the GNU General Public License version 2. This program
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * is licensed "as is" without any warranty of any kind, whether express
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #ifndef _FSL_DDR_EDAC_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define _FSL_DDR_EDAC_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define fsl_mc_printk(mci, level, fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) edac_mc_chipset_printk(mci, level, "FSL_DDR", fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * DRAM error defines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* DDR_SDRAM_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define FSL_MC_DDR_SDRAM_CFG 0x0110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define FSL_MC_CS_BNDS_0 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define FSL_MC_CS_BNDS_OFS 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define FSL_MC_DATA_ERR_INJECT_HI 0x0e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define FSL_MC_DATA_ERR_INJECT_LO 0x0e04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define FSL_MC_ECC_ERR_INJECT 0x0e08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define FSL_MC_CAPTURE_DATA_HI 0x0e20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define FSL_MC_CAPTURE_DATA_LO 0x0e24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define FSL_MC_CAPTURE_ECC 0x0e28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define FSL_MC_ERR_DETECT 0x0e40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define FSL_MC_ERR_DISABLE 0x0e44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define FSL_MC_ERR_INT_EN 0x0e48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define FSL_MC_CAPTURE_ATRIBUTES 0x0e4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define FSL_MC_CAPTURE_ADDRESS 0x0e50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define FSL_MC_CAPTURE_EXT_ADDRESS 0x0e54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define FSL_MC_ERR_SBE 0x0e58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DSC_MEM_EN 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DSC_ECC_EN 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DSC_RD_EN 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DSC_DBW_MASK 0x00180000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DSC_DBW_32 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DSC_DBW_64 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DSC_SDTYPE_MASK 0x07000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DSC_X32_EN 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* Err_Int_En */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DDR_EIE_MSEE 0x1 /* memory select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DDR_EIE_SBEE 0x4 /* single-bit ECC error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DDR_EIE_MBEE 0x8 /* multi-bit ECC error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Err_Detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DDR_EDE_MSE 0x1 /* memory select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DDR_EDE_SBE 0x4 /* single-bit ECC error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DDR_EDE_MBE 0x8 /* multi-bit ECC error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DDR_EDE_MME 0x80000000 /* multiple memory errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* Err_Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DDR_EDI_MSED 0x1 /* memory select disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DDR_EDI_SBED 0x4 /* single-bit ECC error disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DDR_EDI_MBED 0x8 /* multi-bit ECC error disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct fsl_mc_pdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int edac_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) void __iomem *mc_vbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int fsl_mc_err_probe(struct platform_device *op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int fsl_mc_err_remove(struct platform_device *op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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