^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Freescale Memory Controller kernel module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Support Power-based SoCs including MPC85xx, MPC86xx, MPC83xx and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * ARM-based Layerscape SoCs including LS2xxx and LS1021A. Originally
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * split out from mpc85xx_edac EDAC driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Parts Copyrighted (c) 2013 by Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Author: Dave Jiang <djiang@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * the terms of the GNU General Public License version 2. This program
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * is licensed "as is" without any warranty of any kind, whether express
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/ctype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/edac.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/gfp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "edac_module.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "fsl_ddr_edac.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define EDAC_MOD_STR "fsl_ddr_edac"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static int edac_mc_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static u32 orig_ddr_err_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static u32 orig_ddr_err_sbe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static bool little_endian;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static inline u32 ddr_in32(void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return little_endian ? ioread32(addr) : ioread32be(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static inline void ddr_out32(void __iomem *addr, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) if (little_endian)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) iowrite32(value, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) iowrite32be(value, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #ifdef CONFIG_EDAC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /************************ MC SYSFS parts ***********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define to_mci(k) container_of(k, struct mem_ctl_info, dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static ssize_t fsl_mc_inject_data_hi_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct device_attribute *mattr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) char *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct mem_ctl_info *mci = to_mci(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct fsl_mc_pdata *pdata = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return sprintf(data, "0x%08x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) ddr_in32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_HI));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static ssize_t fsl_mc_inject_data_lo_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct device_attribute *mattr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) char *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct mem_ctl_info *mci = to_mci(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct fsl_mc_pdata *pdata = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return sprintf(data, "0x%08x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ddr_in32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_LO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static ssize_t fsl_mc_inject_ctrl_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct device_attribute *mattr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) char *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct mem_ctl_info *mci = to_mci(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct fsl_mc_pdata *pdata = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return sprintf(data, "0x%08x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ddr_in32(pdata->mc_vbase + FSL_MC_ECC_ERR_INJECT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static ssize_t fsl_mc_inject_data_hi_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct device_attribute *mattr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) const char *data, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct mem_ctl_info *mci = to_mci(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct fsl_mc_pdata *pdata = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (isdigit(*data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) rc = kstrtoul(data, 0, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ddr_out32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_HI, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static ssize_t fsl_mc_inject_data_lo_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct device_attribute *mattr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) const char *data, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct mem_ctl_info *mci = to_mci(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct fsl_mc_pdata *pdata = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (isdigit(*data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) rc = kstrtoul(data, 0, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ddr_out32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_LO, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static ssize_t fsl_mc_inject_ctrl_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct device_attribute *mattr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) const char *data, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct mem_ctl_info *mci = to_mci(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct fsl_mc_pdata *pdata = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (isdigit(*data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) rc = kstrtoul(data, 0, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ddr_out32(pdata->mc_vbase + FSL_MC_ECC_ERR_INJECT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static DEVICE_ATTR(inject_data_hi, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) fsl_mc_inject_data_hi_show, fsl_mc_inject_data_hi_store);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static DEVICE_ATTR(inject_data_lo, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) fsl_mc_inject_data_lo_show, fsl_mc_inject_data_lo_store);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static DEVICE_ATTR(inject_ctrl, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) fsl_mc_inject_ctrl_show, fsl_mc_inject_ctrl_store);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #endif /* CONFIG_EDAC_DEBUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static struct attribute *fsl_ddr_dev_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #ifdef CONFIG_EDAC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) &dev_attr_inject_data_hi.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) &dev_attr_inject_data_lo.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) &dev_attr_inject_ctrl.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ATTRIBUTE_GROUPS(fsl_ddr_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /**************************** MC Err device ***************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * Taken from table 8-55 in the MPC8641 User's Manual and/or 9-61 in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * MPC8572 User's Manual. Each line represents a syndrome bit column as a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * 64-bit value, but split into an upper and lower 32-bit chunk. The labels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * below correspond to Freescale's manuals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static unsigned int ecc_table[16] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* MSB LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* [0:31] [32:63] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 0xf00fe11e, 0xc33c0ff7, /* Syndrome bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 0x00ff00ff, 0x00fff0ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 0x0f0f0f0f, 0x0f0fff00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 0x11113333, 0x7777000f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 0x22224444, 0x8888222f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 0x44448888, 0xffff4441,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 0x8888ffff, 0x11118882,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 0xffff1111, 0x22221114, /* Syndrome bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * Calculate the correct ECC value for a 64-bit value specified by high:low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static u8 calculate_ecc(u32 high, u32 low)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u32 mask_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u32 mask_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) int bit_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u8 ecc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) mask_high = ecc_table[i * 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) mask_low = ecc_table[i * 2 + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) bit_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) for (j = 0; j < 32; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if ((mask_high >> j) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) bit_cnt ^= (high >> j) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if ((mask_low >> j) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) bit_cnt ^= (low >> j) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ecc |= bit_cnt << i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return ecc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * Create the syndrome code which is generated if the data line specified by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * 'bit' failed. Eg generate an 8-bit codes seen in Table 8-55 in the MPC8641
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * User's Manual and 9-61 in the MPC8572 User's Manual.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static u8 syndrome_from_bit(unsigned int bit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u8 syndrome = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * Cycle through the upper or lower 32-bit portion of each value in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * ecc_table depending on if 'bit' is in the upper or lower half of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * 64-bit data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) for (i = bit < 32; i < 16; i += 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) syndrome |= ((ecc_table[i] >> (bit % 32)) & 1) << (i / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return syndrome;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * Decode data and ecc syndrome to determine what went wrong
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * Note: This can only decode single-bit errors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static void sbe_ecc_decode(u32 cap_high, u32 cap_low, u32 cap_ecc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) int *bad_data_bit, int *bad_ecc_bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u8 syndrome;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) *bad_data_bit = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) *bad_ecc_bit = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * Calculate the ECC of the captured data and XOR it with the captured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * ECC to find an ECC syndrome value we can search for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) syndrome = calculate_ecc(cap_high, cap_low) ^ cap_ecc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* Check if a data line is stuck... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) for (i = 0; i < 64; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (syndrome == syndrome_from_bit(i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) *bad_data_bit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* If data is correct, check ECC bits for errors... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if ((syndrome >> i) & 0x1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) *bad_ecc_bit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define make64(high, low) (((u64)(high) << 32) | (low))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static void fsl_mc_check(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct fsl_mc_pdata *pdata = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct csrow_info *csrow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) u32 bus_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u32 err_detect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u32 syndrome;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u64 err_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u32 pfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) int row_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) u32 cap_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) u32 cap_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) int bad_data_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) int bad_ecc_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) err_detect = ddr_in32(pdata->mc_vbase + FSL_MC_ERR_DETECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (!err_detect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) fsl_mc_printk(mci, KERN_ERR, "Err Detect Register: %#8.8x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) err_detect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* no more processing if not ECC bit errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (!(err_detect & (DDR_EDE_SBE | DDR_EDE_MBE))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DETECT, err_detect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) syndrome = ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_ECC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* Mask off appropriate bits of syndrome based on bus width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) bus_width = (ddr_in32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) DSC_DBW_MASK) ? 32 : 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (bus_width == 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) syndrome &= 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) syndrome &= 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) err_addr = make64(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_EXT_ADDRESS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_ADDRESS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) pfn = err_addr >> PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) for (row_index = 0; row_index < mci->nr_csrows; row_index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) csrow = mci->csrows[row_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if ((pfn >= csrow->first_page) && (pfn <= csrow->last_page))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) cap_high = ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_DATA_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) cap_low = ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_DATA_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * Analyze single-bit errors on 64-bit wide buses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * TODO: Add support for 32-bit wide buses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if ((err_detect & DDR_EDE_SBE) && (bus_width == 64)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) sbe_ecc_decode(cap_high, cap_low, syndrome,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) &bad_data_bit, &bad_ecc_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (bad_data_bit != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) fsl_mc_printk(mci, KERN_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) "Faulty Data bit: %d\n", bad_data_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (bad_ecc_bit != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) fsl_mc_printk(mci, KERN_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) "Faulty ECC bit: %d\n", bad_ecc_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) fsl_mc_printk(mci, KERN_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) "Expected Data / ECC:\t%#8.8x_%08x / %#2.2x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) cap_high ^ (1 << (bad_data_bit - 32)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) cap_low ^ (1 << bad_data_bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) syndrome ^ (1 << bad_ecc_bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) fsl_mc_printk(mci, KERN_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) "Captured Data / ECC:\t%#8.8x_%08x / %#2.2x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) cap_high, cap_low, syndrome);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) fsl_mc_printk(mci, KERN_ERR, "Err addr: %#8.8llx\n", err_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) fsl_mc_printk(mci, KERN_ERR, "PFN: %#8.8x\n", pfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* we are out of range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (row_index == mci->nr_csrows)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) fsl_mc_printk(mci, KERN_ERR, "PFN out of range!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (err_detect & DDR_EDE_SBE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) pfn, err_addr & ~PAGE_MASK, syndrome,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) row_index, 0, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) mci->ctl_name, "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (err_detect & DDR_EDE_MBE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) pfn, err_addr & ~PAGE_MASK, syndrome,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) row_index, 0, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) mci->ctl_name, "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DETECT, err_detect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static irqreturn_t fsl_mc_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct mem_ctl_info *mci = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct fsl_mc_pdata *pdata = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) u32 err_detect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) err_detect = ddr_in32(pdata->mc_vbase + FSL_MC_ERR_DETECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (!err_detect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) fsl_mc_check(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static void fsl_ddr_init_csrows(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct fsl_mc_pdata *pdata = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct csrow_info *csrow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct dimm_info *dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) u32 sdram_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) u32 sdtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) enum mem_type mtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) u32 cs_bnds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) sdram_ctl = ddr_in32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) sdtype = sdram_ctl & DSC_SDTYPE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (sdram_ctl & DSC_RD_EN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) switch (sdtype) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) case 0x02000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) mtype = MEM_RDDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) case 0x03000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) mtype = MEM_RDDR2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) case 0x07000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) mtype = MEM_RDDR3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) case 0x05000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) mtype = MEM_RDDR4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) mtype = MEM_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) switch (sdtype) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) case 0x02000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) mtype = MEM_DDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) case 0x03000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) mtype = MEM_DDR2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) case 0x07000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) mtype = MEM_DDR3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) case 0x05000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) mtype = MEM_DDR4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) mtype = MEM_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) for (index = 0; index < mci->nr_csrows; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) u32 start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) u32 end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) csrow = mci->csrows[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) dimm = csrow->channels[0]->dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) cs_bnds = ddr_in32(pdata->mc_vbase + FSL_MC_CS_BNDS_0 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) (index * FSL_MC_CS_BNDS_OFS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) start = (cs_bnds & 0xffff0000) >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) end = (cs_bnds & 0x0000ffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (start == end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) continue; /* not populated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) start <<= (24 - PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) end <<= (24 - PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) end |= (1 << (24 - PAGE_SHIFT)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) csrow->first_page = start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) csrow->last_page = end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) dimm->nr_pages = end + 1 - start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) dimm->grain = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) dimm->mtype = mtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) dimm->dtype = DEV_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (sdram_ctl & DSC_X32_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) dimm->dtype = DEV_X32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) dimm->edac_mode = EDAC_SECDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) int fsl_mc_err_probe(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) struct mem_ctl_info *mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) struct edac_mc_layer layers[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct fsl_mc_pdata *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct resource r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) u32 sdram_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (!devres_open_group(&op->dev, fsl_mc_err_probe, GFP_KERNEL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) layers[0].size = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) layers[0].is_virt_csrow = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) layers[1].type = EDAC_MC_LAYER_CHANNEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) layers[1].size = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) layers[1].is_virt_csrow = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) mci = edac_mc_alloc(edac_mc_idx, ARRAY_SIZE(layers), layers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) sizeof(*pdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (!mci) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) devres_release_group(&op->dev, fsl_mc_err_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) pdata = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) pdata->name = "fsl_mc_err";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) mci->pdev = &op->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) pdata->edac_idx = edac_mc_idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) dev_set_drvdata(mci->pdev, mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) mci->ctl_name = pdata->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) mci->dev_name = pdata->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * Get the endianness of DDR controller registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * Default is big endian.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) little_endian = of_property_read_bool(op->dev.of_node, "little-endian");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) res = of_address_to_resource(op->dev.of_node, 0, &r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) pr_err("%s: Unable to get resource for MC err regs\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) pdata->name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) pr_err("%s: Error while requesting mem region\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) res = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) pdata->mc_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (!pdata->mc_vbase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) pr_err("%s: Unable to setup MC err regs\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) res = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) sdram_ctl = ddr_in32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (!(sdram_ctl & DSC_ECC_EN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /* no ECC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) pr_warn("%s: No ECC DIMMs discovered\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) res = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) edac_dbg(3, "init mci\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) mci->mtype_cap = MEM_FLAG_DDR | MEM_FLAG_RDDR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) MEM_FLAG_DDR2 | MEM_FLAG_RDDR2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) MEM_FLAG_DDR3 | MEM_FLAG_RDDR3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) MEM_FLAG_DDR4 | MEM_FLAG_RDDR4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) mci->edac_cap = EDAC_FLAG_SECDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) mci->mod_name = EDAC_MOD_STR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (edac_op_state == EDAC_OPSTATE_POLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) mci->edac_check = fsl_mc_check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) mci->ctl_page_to_phys = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) mci->scrub_mode = SCRUB_SW_SRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) fsl_ddr_init_csrows(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /* store the original error disable bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) orig_ddr_err_disable = ddr_in32(pdata->mc_vbase + FSL_MC_ERR_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DISABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /* clear all error bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DETECT, ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) res = edac_mc_add_mc_with_groups(mci, fsl_ddr_dev_groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) edac_dbg(3, "failed edac_mc_add_mc()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (edac_op_state == EDAC_OPSTATE_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) ddr_out32(pdata->mc_vbase + FSL_MC_ERR_INT_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) DDR_EIE_MBEE | DDR_EIE_SBEE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /* store the original error management threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) orig_ddr_err_sbe = ddr_in32(pdata->mc_vbase +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) FSL_MC_ERR_SBE) & 0xff0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /* set threshold to 1 error per interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) ddr_out32(pdata->mc_vbase + FSL_MC_ERR_SBE, 0x10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* register interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) pdata->irq = platform_get_irq(op, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) res = devm_request_irq(&op->dev, pdata->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) fsl_mc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) "[EDAC] MC err", mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (res < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) pr_err("%s: Unable to request irq %d for FSL DDR DRAM ERR\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) __func__, pdata->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) res = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) goto err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) pr_info(EDAC_MOD_STR " acquired irq %d for MC\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) pdata->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) devres_remove_group(&op->dev, fsl_mc_err_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) edac_dbg(3, "success\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) pr_info(EDAC_MOD_STR " MC err registered\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) err2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) edac_mc_del_mc(&op->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) devres_release_group(&op->dev, fsl_mc_err_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) int fsl_mc_err_remove(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct mem_ctl_info *mci = dev_get_drvdata(&op->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) struct fsl_mc_pdata *pdata = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) edac_dbg(0, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (edac_op_state == EDAC_OPSTATE_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) ddr_out32(pdata->mc_vbase + FSL_MC_ERR_INT_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) orig_ddr_err_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) ddr_out32(pdata->mc_vbase + FSL_MC_ERR_SBE, orig_ddr_err_sbe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) edac_mc_del_mc(&op->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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