Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * EDAC PCI component
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Author: Dave Jiang <djiang@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * 2007 (c) MontaVista Software, Inc. This file is licensed under
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * the terms of the GNU General Public License version 2. This program
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * is licensed "as is" without any warranty of any kind, whether express
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/ctype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/highmem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/sysctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include "edac_pci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include "edac_module.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) static DEFINE_MUTEX(edac_pci_ctls_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) static LIST_HEAD(edac_pci_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) static atomic_t pci_indexes = ATOMIC_INIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) struct edac_pci_ctl_info *edac_pci_alloc_ctl_info(unsigned int sz_pvt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 						const char *edac_pci_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	struct edac_pci_ctl_info *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	void *p = NULL, *pvt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	unsigned int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	edac_dbg(1, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	pci = edac_align_ptr(&p, sizeof(*pci), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	pvt = edac_align_ptr(&p, 1, sz_pvt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	size = ((unsigned long)pvt) + sz_pvt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	/* Alloc the needed control struct memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	pci = kzalloc(size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	if (pci  == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	/* Now much private space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	pvt = sz_pvt ? ((char *)pci) + ((unsigned long)pvt) : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	pci->pvt_info = pvt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	pci->op_state = OP_ALLOC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	snprintf(pci->name, strlen(edac_pci_name) + 1, "%s", edac_pci_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	return pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) EXPORT_SYMBOL_GPL(edac_pci_alloc_ctl_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) void edac_pci_free_ctl_info(struct edac_pci_ctl_info *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	edac_dbg(1, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	edac_pci_remove_sysfs(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) EXPORT_SYMBOL_GPL(edac_pci_free_ctl_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  * find_edac_pci_by_dev()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)  * 	scans the edac_pci list for a specific 'struct device *'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73)  *	return NULL if not found, or return control struct pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static struct edac_pci_ctl_info *find_edac_pci_by_dev(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	struct edac_pci_ctl_info *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	struct list_head *item;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	edac_dbg(1, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	list_for_each(item, &edac_pci_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		pci = list_entry(item, struct edac_pci_ctl_info, link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		if (pci->dev == dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 			return pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93)  * add_edac_pci_to_global_list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94)  * 	Before calling this function, caller must assign a unique value to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95)  * 	edac_dev->pci_idx.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96)  * 	Return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97)  * 		0 on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98)  * 		1 on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static int add_edac_pci_to_global_list(struct edac_pci_ctl_info *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	struct list_head *item, *insert_before;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	struct edac_pci_ctl_info *rover;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	edac_dbg(1, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	insert_before = &edac_pci_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	/* Determine if already on the list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	rover = find_edac_pci_by_dev(pci->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	if (unlikely(rover != NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		goto fail0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	/* Insert in ascending order by 'pci_idx', so find position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	list_for_each(item, &edac_pci_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		rover = list_entry(item, struct edac_pci_ctl_info, link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		if (rover->pci_idx >= pci->pci_idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 			if (unlikely(rover->pci_idx == pci->pci_idx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 				goto fail1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 			insert_before = item;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	list_add_tail_rcu(&pci->link, insert_before);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) fail0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	edac_printk(KERN_WARNING, EDAC_PCI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		"%s (%s) %s %s already assigned %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		dev_name(rover->dev), edac_dev_name(rover),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		rover->mod_name, rover->ctl_name, rover->pci_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) fail1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	edac_printk(KERN_WARNING, EDAC_PCI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		"but in low-level driver: attempt to assign\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		"\tduplicate pci_idx %d in %s()\n", rover->pci_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		__func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)  * del_edac_pci_from_global_list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)  *	remove the PCI control struct from the global list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static void del_edac_pci_from_global_list(struct edac_pci_ctl_info *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	list_del_rcu(&pci->link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	/* these are for safe removal of devices from global list while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	 * NMI handlers may be traversing list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	synchronize_rcu();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	INIT_LIST_HEAD(&pci->link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)  * edac_pci_workq_function()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)  * 	periodic function that performs the operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)  *	scheduled by a workq request, for a given PCI control struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static void edac_pci_workq_function(struct work_struct *work_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	struct delayed_work *d_work = to_delayed_work(work_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	struct edac_pci_ctl_info *pci = to_edac_pci_ctl_work(d_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	int msec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	unsigned long delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	edac_dbg(3, "checking\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	mutex_lock(&edac_pci_ctls_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	if (pci->op_state != OP_RUNNING_POLL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		mutex_unlock(&edac_pci_ctls_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	if (edac_pci_get_check_errors())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		pci->edac_check(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	/* if we are on a one second period, then use round */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	msec = edac_pci_get_poll_msec();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	if (msec == 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		delay = round_jiffies_relative(msecs_to_jiffies(msec));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		delay = msecs_to_jiffies(msec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	edac_queue_work(&pci->work, delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	mutex_unlock(&edac_pci_ctls_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int edac_pci_alloc_index(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	return atomic_inc_return(&pci_indexes) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) EXPORT_SYMBOL_GPL(edac_pci_alloc_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) int edac_pci_add_device(struct edac_pci_ctl_info *pci, int edac_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	edac_dbg(0, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	pci->pci_idx = edac_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	pci->start_time = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	mutex_lock(&edac_pci_ctls_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	if (add_edac_pci_to_global_list(pci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		goto fail0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	if (edac_pci_create_sysfs(pci)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		edac_pci_printk(pci, KERN_WARNING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 				"failed to create sysfs pci\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		goto fail1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	if (pci->edac_check) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		pci->op_state = OP_RUNNING_POLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		INIT_DELAYED_WORK(&pci->work, edac_pci_workq_function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		edac_queue_work(&pci->work, msecs_to_jiffies(edac_pci_get_poll_msec()));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		pci->op_state = OP_RUNNING_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	edac_pci_printk(pci, KERN_INFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		"Giving out device to module %s controller %s: DEV %s (%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		pci->mod_name, pci->ctl_name, pci->dev_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		edac_op_state_to_string(pci->op_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	mutex_unlock(&edac_pci_ctls_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	/* error unwind stack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) fail1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	del_edac_pci_from_global_list(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) fail0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	mutex_unlock(&edac_pci_ctls_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) EXPORT_SYMBOL_GPL(edac_pci_add_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct edac_pci_ctl_info *edac_pci_del_device(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	struct edac_pci_ctl_info *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	edac_dbg(0, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	mutex_lock(&edac_pci_ctls_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	/* ensure the control struct is on the global list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	 * if not, then leave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	pci = find_edac_pci_by_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	if (pci  == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		mutex_unlock(&edac_pci_ctls_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	pci->op_state = OP_OFFLINE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	del_edac_pci_from_global_list(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	mutex_unlock(&edac_pci_ctls_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	if (pci->edac_check)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		edac_stop_work(&pci->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	edac_printk(KERN_INFO, EDAC_PCI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		"Removed device %d for %s %s: DEV %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		pci->pci_idx, pci->mod_name, pci->ctl_name, edac_dev_name(pci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	return pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) EXPORT_SYMBOL_GPL(edac_pci_del_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)  * edac_pci_generic_check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)  *	a Generic parity check API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static void edac_pci_generic_check(struct edac_pci_ctl_info *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	edac_dbg(4, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	edac_pci_do_parity_check();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* free running instance index counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static int edac_pci_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define EDAC_PCI_GENCTL_NAME	"EDAC PCI controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct edac_pci_gen_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	int edac_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct edac_pci_ctl_info *edac_pci_create_generic_ctl(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 						const char *mod_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	struct edac_pci_ctl_info *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	struct edac_pci_gen_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	pci = edac_pci_alloc_ctl_info(sizeof(*pdata), EDAC_PCI_GENCTL_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	if (!pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	pdata = pci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	pci->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	dev_set_drvdata(pci->dev, pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	pci->dev_name = pci_name(to_pci_dev(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	pci->mod_name = mod_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	pci->ctl_name = EDAC_PCI_GENCTL_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	if (edac_op_state == EDAC_OPSTATE_POLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		pci->edac_check = edac_pci_generic_check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	pdata->edac_idx = edac_pci_idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	if (edac_pci_add_device(pci, pdata->edac_idx) > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		edac_dbg(3, "failed edac_pci_add_device()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		edac_pci_free_ctl_info(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	return pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) EXPORT_SYMBOL_GPL(edac_pci_create_generic_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) void edac_pci_release_generic_ctl(struct edac_pci_ctl_info *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	edac_dbg(0, "pci mod=%s\n", pci->mod_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	edac_pci_del_device(pci->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	edac_pci_free_ctl_info(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) EXPORT_SYMBOL_GPL(edac_pci_release_generic_ctl);