^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * edac_mc kernel module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * (C) 2005, 2006 Linux Networx (http://lnxi.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This file may be distributed under the terms of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * GNU General Public License.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Written by Thayne Harbaugh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on work by Dan Hollis <goemon at anime dot net> and others.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * http://www.anime.net/~goemon/linux-ecc/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Modified by Dave Peterson and Doug Thompson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/proc_fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/sysctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/highmem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/ctype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/edac.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "edac_mc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "edac_module.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <ras/ras_event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #ifdef CONFIG_EDAC_ATOMIC_SCRUB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <asm/edac.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define edac_atomic_scrub(va, size) do { } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) int edac_op_state = EDAC_OPSTATE_INVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) EXPORT_SYMBOL_GPL(edac_op_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* lock to memory controller's control array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static DEFINE_MUTEX(mem_ctls_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static LIST_HEAD(mc_devices);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * Used to lock EDAC MC to just one module, avoiding two drivers e. g.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * apei/ghes and i7core_edac to be used at the same time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static const char *edac_mc_owner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static struct mem_ctl_info *error_desc_to_mci(struct edac_raw_error_desc *e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return container_of(e, struct mem_ctl_info, error_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned int edac_dimm_info_location(struct dimm_info *dimm, char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct mem_ctl_info *mci = dimm->mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int i, n, count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) char *p = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) for (i = 0; i < mci->n_layers; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) n = snprintf(p, len, "%s %d ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) edac_layer_name[mci->layers[i].type],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) dimm->location[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) p += n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) len -= n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) count += n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (!len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #ifdef CONFIG_EDAC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static void edac_mc_dump_channel(struct rank_info *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) edac_dbg(4, " channel->chan_idx = %d\n", chan->chan_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) edac_dbg(4, " channel = %p\n", chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) edac_dbg(4, " channel->csrow = %p\n", chan->csrow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) edac_dbg(4, " channel->dimm = %p\n", chan->dimm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static void edac_mc_dump_dimm(struct dimm_info *dimm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) char location[80];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (!dimm->nr_pages)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) edac_dimm_info_location(dimm, location, sizeof(location));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) edac_dbg(4, "%s%i: %smapped as virtual row %d, chan %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) dimm->mci->csbased ? "rank" : "dimm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) dimm->idx, location, dimm->csrow, dimm->cschannel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) edac_dbg(4, " dimm = %p\n", dimm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) edac_dbg(4, " dimm->label = '%s'\n", dimm->label);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) edac_dbg(4, " dimm->nr_pages = 0x%x\n", dimm->nr_pages);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) edac_dbg(4, " dimm->grain = %d\n", dimm->grain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) edac_dbg(4, " dimm->nr_pages = 0x%x\n", dimm->nr_pages);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static void edac_mc_dump_csrow(struct csrow_info *csrow)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) edac_dbg(4, "csrow->csrow_idx = %d\n", csrow->csrow_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) edac_dbg(4, " csrow = %p\n", csrow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) edac_dbg(4, " csrow->first_page = 0x%lx\n", csrow->first_page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) edac_dbg(4, " csrow->last_page = 0x%lx\n", csrow->last_page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) edac_dbg(4, " csrow->page_mask = 0x%lx\n", csrow->page_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) edac_dbg(4, " csrow->nr_channels = %d\n", csrow->nr_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) edac_dbg(4, " csrow->channels = %p\n", csrow->channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) edac_dbg(4, " csrow->mci = %p\n", csrow->mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static void edac_mc_dump_mci(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) edac_dbg(3, "\tmci = %p\n", mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) edac_dbg(3, "\tmci->mtype_cap = %lx\n", mci->mtype_cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) edac_dbg(3, "\tmci->edac_ctl_cap = %lx\n", mci->edac_ctl_cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) edac_dbg(3, "\tmci->edac_cap = %lx\n", mci->edac_cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) edac_dbg(4, "\tmci->edac_check = %p\n", mci->edac_check);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) edac_dbg(3, "\tmci->nr_csrows = %d, csrows = %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) mci->nr_csrows, mci->csrows);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) edac_dbg(3, "\tmci->nr_dimms = %d, dimms = %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) mci->tot_dimms, mci->dimms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) edac_dbg(3, "\tdev = %p\n", mci->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) edac_dbg(3, "\tmod_name:ctl_name = %s:%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) mci->mod_name, mci->ctl_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) edac_dbg(3, "\tpvt_info = %p\n\n", mci->pvt_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #endif /* CONFIG_EDAC_DEBUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) const char * const edac_mem_types[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) [MEM_EMPTY] = "Empty",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) [MEM_RESERVED] = "Reserved",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) [MEM_UNKNOWN] = "Unknown",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) [MEM_FPM] = "FPM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) [MEM_EDO] = "EDO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) [MEM_BEDO] = "BEDO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) [MEM_SDR] = "Unbuffered-SDR",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) [MEM_RDR] = "Registered-SDR",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) [MEM_DDR] = "Unbuffered-DDR",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) [MEM_RDDR] = "Registered-DDR",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) [MEM_RMBS] = "RMBS",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) [MEM_DDR2] = "Unbuffered-DDR2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) [MEM_FB_DDR2] = "FullyBuffered-DDR2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) [MEM_RDDR2] = "Registered-DDR2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) [MEM_XDR] = "XDR",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) [MEM_DDR3] = "Unbuffered-DDR3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) [MEM_RDDR3] = "Registered-DDR3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) [MEM_LRDDR3] = "Load-Reduced-DDR3-RAM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) [MEM_DDR4] = "Unbuffered-DDR4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) [MEM_RDDR4] = "Registered-DDR4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) [MEM_LRDDR4] = "Load-Reduced-DDR4-RAM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) [MEM_NVDIMM] = "Non-volatile-RAM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) EXPORT_SYMBOL_GPL(edac_mem_types);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * edac_align_ptr - Prepares the pointer offsets for a single-shot allocation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * @p: pointer to a pointer with the memory offset to be used. At
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * return, this will be incremented to point to the next offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * @size: Size of the data structure to be reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * @n_elems: Number of elements that should be reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * If 'size' is a constant, the compiler will optimize this whole function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * down to either a no-op or the addition of a constant to the value of '*p'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * The 'p' pointer is absolutely needed to keep the proper advancing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * further in memory to the proper offsets when allocating the struct along
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * with its embedded structs, as edac_device_alloc_ctl_info() does it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * above, for example.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * At return, the pointer 'p' will be incremented to be used on a next call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * to this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) void *edac_align_ptr(void **p, unsigned int size, int n_elems)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) unsigned int align, r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) void *ptr = *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) *p += size * n_elems;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * 'p' can possibly be an unaligned item X such that sizeof(X) is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * 'size'. Adjust 'p' so that its alignment is at least as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * stringent as what the compiler would provide for X and return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * the aligned result.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * Here we assume that the alignment of a "long long" is the most
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * stringent alignment that the compiler will ever provide by default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * As far as I know, this is a reasonable assumption.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (size > sizeof(long))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) align = sizeof(long long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) else if (size > sizeof(int))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) align = sizeof(long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) else if (size > sizeof(short))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) align = sizeof(int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) else if (size > sizeof(char))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) align = sizeof(short);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return (char *)ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) r = (unsigned long)ptr % align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (r == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return (char *)ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) *p += align - r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return (void *)(((unsigned long)ptr) + align - r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static void _edac_mc_free(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) put_device(&mci->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static void mci_release(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct mem_ctl_info *mci = container_of(dev, struct mem_ctl_info, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct csrow_info *csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int i, chn, row;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (mci->dimms) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) for (i = 0; i < mci->tot_dimms; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) kfree(mci->dimms[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) kfree(mci->dimms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (mci->csrows) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) for (row = 0; row < mci->nr_csrows; row++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) csr = mci->csrows[row];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (!csr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (csr->channels) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) for (chn = 0; chn < mci->num_cschannel; chn++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) kfree(csr->channels[chn]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) kfree(csr->channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) kfree(csr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) kfree(mci->csrows);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) kfree(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static int edac_mc_alloc_csrows(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) unsigned int tot_channels = mci->num_cschannel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) unsigned int tot_csrows = mci->nr_csrows;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned int row, chn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * Alocate and fill the csrow/channels structs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) mci->csrows = kcalloc(tot_csrows, sizeof(*mci->csrows), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (!mci->csrows)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) for (row = 0; row < tot_csrows; row++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct csrow_info *csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) csr = kzalloc(sizeof(**mci->csrows), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (!csr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) mci->csrows[row] = csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) csr->csrow_idx = row;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) csr->mci = mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) csr->nr_channels = tot_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) csr->channels = kcalloc(tot_channels, sizeof(*csr->channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (!csr->channels)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) for (chn = 0; chn < tot_channels; chn++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct rank_info *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) chan = kzalloc(sizeof(**csr->channels), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (!chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) csr->channels[chn] = chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) chan->chan_idx = chn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) chan->csrow = csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static int edac_mc_alloc_dimms(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) unsigned int pos[EDAC_MAX_LAYERS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) unsigned int row, chn, idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) int layer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) void *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * Allocate and fill the dimm structs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) mci->dimms = kcalloc(mci->tot_dimms, sizeof(*mci->dimms), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (!mci->dimms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) memset(&pos, 0, sizeof(pos));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) row = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) chn = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) for (idx = 0; idx < mci->tot_dimms; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct dimm_info *dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct rank_info *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) int n, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) chan = mci->csrows[row]->channels[chn];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) dimm = kzalloc(sizeof(**mci->dimms), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (!dimm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) mci->dimms[idx] = dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) dimm->mci = mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) dimm->idx = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * Copy DIMM location and initialize it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) len = sizeof(dimm->label);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) p = dimm->label;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) n = snprintf(p, len, "mc#%u", mci->mc_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) p += n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) len -= n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) for (layer = 0; layer < mci->n_layers; layer++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) n = snprintf(p, len, "%s#%u",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) edac_layer_name[mci->layers[layer].type],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) pos[layer]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) p += n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) len -= n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) dimm->location[layer] = pos[layer];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (len <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* Link it to the csrows old API data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) chan->dimm = dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) dimm->csrow = row;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) dimm->cschannel = chn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* Increment csrow location */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (mci->layers[0].is_virt_csrow) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) chn++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (chn == mci->num_cschannel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) chn = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) row++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) row++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (row == mci->nr_csrows) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) row = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) chn++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* Increment dimm location */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) for (layer = mci->n_layers - 1; layer >= 0; layer--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) pos[layer]++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (pos[layer] < mci->layers[layer].size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) pos[layer] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct mem_ctl_info *edac_mc_alloc(unsigned int mc_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) unsigned int n_layers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct edac_mc_layer *layers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) unsigned int sz_pvt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct mem_ctl_info *mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct edac_mc_layer *layer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) unsigned int idx, size, tot_dimms = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) unsigned int tot_csrows = 1, tot_channels = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) void *pvt, *ptr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) bool per_rank = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (WARN_ON(n_layers > EDAC_MAX_LAYERS || n_layers == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * Calculate the total amount of dimms and csrows/cschannels while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * in the old API emulation mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) for (idx = 0; idx < n_layers; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) tot_dimms *= layers[idx].size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (layers[idx].is_virt_csrow)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) tot_csrows *= layers[idx].size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) tot_channels *= layers[idx].size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (layers[idx].type == EDAC_MC_LAYER_CHIP_SELECT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) per_rank = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* Figure out the offsets of the various items from the start of an mc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * structure. We want the alignment of each item to be at least as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * stringent as what the compiler would provide if we could simply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * hardcode everything into a single struct.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) mci = edac_align_ptr(&ptr, sizeof(*mci), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) layer = edac_align_ptr(&ptr, sizeof(*layer), n_layers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) pvt = edac_align_ptr(&ptr, sz_pvt, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) size = ((unsigned long)pvt) + sz_pvt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) edac_dbg(1, "allocating %u bytes for mci data (%d %s, %d csrows/channels)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) tot_dimms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) per_rank ? "ranks" : "dimms",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) tot_csrows * tot_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) mci = kzalloc(size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (mci == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) mci->dev.release = mci_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) device_initialize(&mci->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* Adjust pointers so they point within the memory we just allocated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * rather than an imaginary chunk of memory located at address 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) layer = (struct edac_mc_layer *)(((char *)mci) + ((unsigned long)layer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) pvt = sz_pvt ? (((char *)mci) + ((unsigned long)pvt)) : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* setup index and various internal pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) mci->mc_idx = mc_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) mci->tot_dimms = tot_dimms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) mci->pvt_info = pvt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) mci->n_layers = n_layers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) mci->layers = layer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) memcpy(mci->layers, layers, sizeof(*layer) * n_layers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) mci->nr_csrows = tot_csrows;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) mci->num_cschannel = tot_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) mci->csbased = per_rank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (edac_mc_alloc_csrows(mci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (edac_mc_alloc_dimms(mci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) mci->op_state = OP_ALLOC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) _edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) EXPORT_SYMBOL_GPL(edac_mc_alloc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) void edac_mc_free(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) edac_dbg(1, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) _edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) EXPORT_SYMBOL_GPL(edac_mc_free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) bool edac_has_mcs(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) bool ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) mutex_lock(&mem_ctls_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) ret = list_empty(&mc_devices);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) mutex_unlock(&mem_ctls_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return !ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) EXPORT_SYMBOL_GPL(edac_has_mcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* Caller must hold mem_ctls_mutex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static struct mem_ctl_info *__find_mci_by_dev(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct mem_ctl_info *mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct list_head *item;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) edac_dbg(3, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) list_for_each(item, &mc_devices) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) mci = list_entry(item, struct mem_ctl_info, link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (mci->pdev == dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * find_mci_by_dev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * scan list of controllers looking for the one that manages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * the 'dev' device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * @dev: pointer to a struct device related with the MCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct mem_ctl_info *find_mci_by_dev(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct mem_ctl_info *ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) mutex_lock(&mem_ctls_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) ret = __find_mci_by_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) mutex_unlock(&mem_ctls_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) EXPORT_SYMBOL_GPL(find_mci_by_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * edac_mc_workq_function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * performs the operation scheduled by a workq request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static void edac_mc_workq_function(struct work_struct *work_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) struct delayed_work *d_work = to_delayed_work(work_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct mem_ctl_info *mci = to_edac_mem_ctl_work(d_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) mutex_lock(&mem_ctls_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (mci->op_state != OP_RUNNING_POLL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) mutex_unlock(&mem_ctls_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (edac_op_state == EDAC_OPSTATE_POLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) mci->edac_check(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) mutex_unlock(&mem_ctls_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /* Queue ourselves again. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) edac_queue_work(&mci->work, msecs_to_jiffies(edac_mc_get_poll_msec()));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * edac_mc_reset_delay_period(unsigned long value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * user space has updated our poll period value, need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * reset our workq delays
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) void edac_mc_reset_delay_period(unsigned long value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) struct mem_ctl_info *mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) struct list_head *item;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) mutex_lock(&mem_ctls_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) list_for_each(item, &mc_devices) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) mci = list_entry(item, struct mem_ctl_info, link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (mci->op_state == OP_RUNNING_POLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) edac_mod_work(&mci->work, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) mutex_unlock(&mem_ctls_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* Return 0 on success, 1 on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) * Before calling this function, caller must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * assign a unique value to mci->mc_idx.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * locking model:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) * called with the mem_ctls_mutex lock held
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static int add_mc_to_global_list(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct list_head *item, *insert_before;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct mem_ctl_info *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) insert_before = &mc_devices;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) p = __find_mci_by_dev(mci->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (unlikely(p != NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) goto fail0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) list_for_each(item, &mc_devices) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) p = list_entry(item, struct mem_ctl_info, link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (p->mc_idx >= mci->mc_idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (unlikely(p->mc_idx == mci->mc_idx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) goto fail1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) insert_before = item;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) list_add_tail_rcu(&mci->link, insert_before);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) fail0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) edac_printk(KERN_WARNING, EDAC_MC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) "%s (%s) %s %s already assigned %d\n", dev_name(p->pdev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) edac_dev_name(mci), p->mod_name, p->ctl_name, p->mc_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) fail1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) edac_printk(KERN_WARNING, EDAC_MC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) "bug in low-level driver: attempt to assign\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) " duplicate mc_idx %d in %s()\n", p->mc_idx, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static int del_mc_from_global_list(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) list_del_rcu(&mci->link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /* these are for safe removal of devices from global list while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * NMI handlers may be traversing list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) synchronize_rcu();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) INIT_LIST_HEAD(&mci->link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return list_empty(&mc_devices);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct mem_ctl_info *edac_mc_find(int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct mem_ctl_info *mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) struct list_head *item;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) mutex_lock(&mem_ctls_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) list_for_each(item, &mc_devices) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) mci = list_entry(item, struct mem_ctl_info, link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (mci->mc_idx == idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) mci = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) mutex_unlock(&mem_ctls_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) EXPORT_SYMBOL(edac_mc_find);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) const char *edac_get_owner(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return edac_mc_owner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) EXPORT_SYMBOL_GPL(edac_get_owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /* FIXME - should a warning be printed if no error detection? correction? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) int edac_mc_add_mc_with_groups(struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) const struct attribute_group **groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) edac_dbg(0, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #ifdef CONFIG_EDAC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (edac_debug_level >= 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) edac_mc_dump_mci(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (edac_debug_level >= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) struct dimm_info *dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) for (i = 0; i < mci->nr_csrows; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) struct csrow_info *csrow = mci->csrows[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) u32 nr_pages = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) for (j = 0; j < csrow->nr_channels; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) nr_pages += csrow->channels[j]->dimm->nr_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (!nr_pages)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) edac_mc_dump_csrow(csrow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) for (j = 0; j < csrow->nr_channels; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (csrow->channels[j]->dimm->nr_pages)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) edac_mc_dump_channel(csrow->channels[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) mci_for_each_dimm(mci, dimm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) edac_mc_dump_dimm(dimm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) mutex_lock(&mem_ctls_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (edac_mc_owner && edac_mc_owner != mci->mod_name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) ret = -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) goto fail0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (add_mc_to_global_list(mci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) goto fail0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) /* set load time so that error rate can be tracked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) mci->start_time = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) mci->bus = edac_get_sysfs_subsys();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (edac_create_sysfs_mci_device(mci, groups)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) edac_mc_printk(mci, KERN_WARNING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) "failed to create sysfs device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) goto fail1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (mci->edac_check) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) mci->op_state = OP_RUNNING_POLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) INIT_DELAYED_WORK(&mci->work, edac_mc_workq_function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) edac_queue_work(&mci->work, msecs_to_jiffies(edac_mc_get_poll_msec()));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) mci->op_state = OP_RUNNING_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) /* Report action taken */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) edac_mc_printk(mci, KERN_INFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) "Giving out device to module %s controller %s: DEV %s (%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) mci->mod_name, mci->ctl_name, mci->dev_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) edac_op_state_to_string(mci->op_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) edac_mc_owner = mci->mod_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) mutex_unlock(&mem_ctls_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) fail1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) del_mc_from_global_list(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) fail0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) mutex_unlock(&mem_ctls_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) EXPORT_SYMBOL_GPL(edac_mc_add_mc_with_groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) struct mem_ctl_info *edac_mc_del_mc(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) struct mem_ctl_info *mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) edac_dbg(0, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) mutex_lock(&mem_ctls_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* find the requested mci struct in the global list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) mci = __find_mci_by_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (mci == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) mutex_unlock(&mem_ctls_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) /* mark MCI offline: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) mci->op_state = OP_OFFLINE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (del_mc_from_global_list(mci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) edac_mc_owner = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) mutex_unlock(&mem_ctls_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (mci->edac_check)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) edac_stop_work(&mci->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /* remove from sysfs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) edac_remove_sysfs_mci_device(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) edac_printk(KERN_INFO, EDAC_MC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) "Removed device %d for %s %s: DEV %s\n", mci->mc_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) mci->mod_name, mci->ctl_name, edac_dev_name(mci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) return mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) EXPORT_SYMBOL_GPL(edac_mc_del_mc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static void edac_mc_scrub_block(unsigned long page, unsigned long offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) u32 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) struct page *pg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) void *virt_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) edac_dbg(3, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) /* ECC error page was not in our memory. Ignore it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (!pfn_valid(page))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) /* Find the actual page structure then map it and fix */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) pg = pfn_to_page(page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (PageHighMem(pg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) virt_addr = kmap_atomic(pg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) /* Perform architecture specific atomic scrub operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) edac_atomic_scrub(virt_addr + offset, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) /* Unmap and complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) kunmap_atomic(virt_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (PageHighMem(pg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) /* FIXME - should return -1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci, unsigned long page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) struct csrow_info **csrows = mci->csrows;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) int row, i, j, n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) edac_dbg(1, "MC%d: 0x%lx\n", mci->mc_idx, page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) row = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) for (i = 0; i < mci->nr_csrows; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) struct csrow_info *csrow = csrows[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) n = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) for (j = 0; j < csrow->nr_channels; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) struct dimm_info *dimm = csrow->channels[j]->dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) n += dimm->nr_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if (n == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) edac_dbg(3, "MC%d: first(0x%lx) page(0x%lx) last(0x%lx) mask(0x%lx)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) mci->mc_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) csrow->first_page, page, csrow->last_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) csrow->page_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) if ((page >= csrow->first_page) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) (page <= csrow->last_page) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) ((page & csrow->page_mask) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) (csrow->first_page & csrow->page_mask))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) row = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (row == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) edac_mc_printk(mci, KERN_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) "could not look up page error address %lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) (unsigned long)page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return row;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) EXPORT_SYMBOL_GPL(edac_mc_find_csrow_by_page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) const char *edac_layer_name[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) [EDAC_MC_LAYER_BRANCH] = "branch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) [EDAC_MC_LAYER_CHANNEL] = "channel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) [EDAC_MC_LAYER_SLOT] = "slot",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) [EDAC_MC_LAYER_CHIP_SELECT] = "csrow",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) [EDAC_MC_LAYER_ALL_MEM] = "memory",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) EXPORT_SYMBOL_GPL(edac_layer_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) static void edac_inc_ce_error(struct edac_raw_error_desc *e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) int pos[EDAC_MAX_LAYERS] = { e->top_layer, e->mid_layer, e->low_layer };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) struct mem_ctl_info *mci = error_desc_to_mci(e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) struct dimm_info *dimm = edac_get_dimm(mci, pos[0], pos[1], pos[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) mci->ce_mc += e->error_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (dimm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) dimm->ce_count += e->error_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) mci->ce_noinfo_count += e->error_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) static void edac_inc_ue_error(struct edac_raw_error_desc *e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) int pos[EDAC_MAX_LAYERS] = { e->top_layer, e->mid_layer, e->low_layer };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) struct mem_ctl_info *mci = error_desc_to_mci(e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) struct dimm_info *dimm = edac_get_dimm(mci, pos[0], pos[1], pos[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) mci->ue_mc += e->error_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (dimm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) dimm->ue_count += e->error_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) mci->ue_noinfo_count += e->error_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) static void edac_ce_error(struct edac_raw_error_desc *e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) struct mem_ctl_info *mci = error_desc_to_mci(e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) unsigned long remapped_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (edac_mc_get_log_ce()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) edac_mc_printk(mci, KERN_WARNING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) "%d CE %s%son %s (%s page:0x%lx offset:0x%lx grain:%ld syndrome:0x%lx%s%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) e->error_count, e->msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) *e->msg ? " " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) e->label, e->location, e->page_frame_number, e->offset_in_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) e->grain, e->syndrome,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) *e->other_detail ? " - " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) e->other_detail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) edac_inc_ce_error(e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (mci->scrub_mode == SCRUB_SW_SRC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) * Some memory controllers (called MCs below) can remap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) * memory so that it is still available at a different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) * address when PCI devices map into memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) * MC's that can't do this, lose the memory where PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) * devices are mapped. This mapping is MC-dependent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) * and so we call back into the MC driver for it to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) * map the MC page to a physical (CPU) page which can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) * then be mapped to a virtual page - which can then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) * be scrubbed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) remapped_page = mci->ctl_page_to_phys ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) mci->ctl_page_to_phys(mci, e->page_frame_number) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) e->page_frame_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) edac_mc_scrub_block(remapped_page, e->offset_in_page, e->grain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) static void edac_ue_error(struct edac_raw_error_desc *e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) struct mem_ctl_info *mci = error_desc_to_mci(e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (edac_mc_get_log_ue()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) edac_mc_printk(mci, KERN_WARNING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) "%d UE %s%son %s (%s page:0x%lx offset:0x%lx grain:%ld%s%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) e->error_count, e->msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) *e->msg ? " " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) e->label, e->location, e->page_frame_number, e->offset_in_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) e->grain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) *e->other_detail ? " - " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) e->other_detail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) edac_inc_ue_error(e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if (edac_mc_get_panic_on_ue()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) panic("UE %s%son %s (%s page:0x%lx offset:0x%lx grain:%ld%s%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) e->msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) *e->msg ? " " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) e->label, e->location, e->page_frame_number, e->offset_in_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) e->grain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) *e->other_detail ? " - " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) e->other_detail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) static void edac_inc_csrow(struct edac_raw_error_desc *e, int row, int chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) struct mem_ctl_info *mci = error_desc_to_mci(e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) enum hw_event_mc_err_type type = e->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) u16 count = e->error_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (row < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) edac_dbg(4, "csrow/channel to increment: (%d,%d)\n", row, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if (type == HW_EVENT_ERR_CORRECTED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) mci->csrows[row]->ce_count += count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if (chan >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) mci->csrows[row]->channels[chan]->ce_count += count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) mci->csrows[row]->ue_count += count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) void edac_raw_mc_handle_error(struct edac_raw_error_desc *e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) struct mem_ctl_info *mci = error_desc_to_mci(e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) u8 grain_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) /* Sanity-check driver-supplied grain value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (WARN_ON_ONCE(!e->grain))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) e->grain = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) grain_bits = fls_long(e->grain - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) /* Report the error via the trace interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) if (IS_ENABLED(CONFIG_RAS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) trace_mc_event(e->type, e->msg, e->label, e->error_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) mci->mc_idx, e->top_layer, e->mid_layer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) e->low_layer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) (e->page_frame_number << PAGE_SHIFT) | e->offset_in_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) grain_bits, e->syndrome, e->other_detail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) if (e->type == HW_EVENT_ERR_CORRECTED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) edac_ce_error(e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) edac_ue_error(e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) EXPORT_SYMBOL_GPL(edac_raw_mc_handle_error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) void edac_mc_handle_error(const enum hw_event_mc_err_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) const u16 error_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) const unsigned long page_frame_number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) const unsigned long offset_in_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) const unsigned long syndrome,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) const int top_layer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) const int mid_layer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) const int low_layer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) const char *msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) const char *other_detail)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) struct dimm_info *dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) char *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) int row = -1, chan = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) int pos[EDAC_MAX_LAYERS] = { top_layer, mid_layer, low_layer };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) int i, n_labels = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) struct edac_raw_error_desc *e = &mci->error_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) bool any_memory = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) edac_dbg(3, "MC%d\n", mci->mc_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) /* Fills the error report buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) memset(e, 0, sizeof (*e));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) e->error_count = error_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) e->type = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) e->top_layer = top_layer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) e->mid_layer = mid_layer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) e->low_layer = low_layer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) e->page_frame_number = page_frame_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) e->offset_in_page = offset_in_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) e->syndrome = syndrome;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) /* need valid strings here for both: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) e->msg = msg ?: "";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) e->other_detail = other_detail ?: "";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) * Check if the event report is consistent and if the memory location is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) * known. If it is, the DIMM(s) label info will be filled and the DIMM's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) * error counters will be incremented.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) for (i = 0; i < mci->n_layers; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) if (pos[i] >= (int)mci->layers[i].size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) edac_mc_printk(mci, KERN_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) "INTERNAL ERROR: %s value is out of range (%d >= %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) edac_layer_name[mci->layers[i].type],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) pos[i], mci->layers[i].size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) * Instead of just returning it, let's use what's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) * known about the error. The increment routines and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) * the DIMM filter logic will do the right thing by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) * pointing the likely damaged DIMMs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) pos[i] = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) if (pos[i] >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) any_memory = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) * Get the dimm label/grain that applies to the match criteria.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) * As the error algorithm may not be able to point to just one memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) * stick, the logic here will get all possible labels that could
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) * pottentially be affected by the error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) * On FB-DIMM memory controllers, for uncorrected errors, it is common
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) * to have only the MC channel and the MC dimm (also called "branch")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) * but the channel is not known, as the memory is arranged in pairs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) * where each memory belongs to a separate channel within the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) * branch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) p = e->label;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) *p = '\0';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) mci_for_each_dimm(mci, dimm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if (top_layer >= 0 && top_layer != dimm->location[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) if (mid_layer >= 0 && mid_layer != dimm->location[1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) if (low_layer >= 0 && low_layer != dimm->location[2])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) /* get the max grain, over the error match range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) if (dimm->grain > e->grain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) e->grain = dimm->grain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) * If the error is memory-controller wide, there's no need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) * seek for the affected DIMMs because the whole channel/memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) * controller/... may be affected. Also, don't show errors for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) * empty DIMM slots.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (!dimm->nr_pages)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) n_labels++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) if (n_labels > EDAC_MAX_LABELS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) p = e->label;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) *p = '\0';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) if (p != e->label) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) strcpy(p, OTHER_LABEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) p += strlen(OTHER_LABEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) strcpy(p, dimm->label);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) p += strlen(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) * get csrow/channel of the DIMM, in order to allow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) * incrementing the compat API counters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) edac_dbg(4, "%s csrows map: (%d,%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) mci->csbased ? "rank" : "dimm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) dimm->csrow, dimm->cschannel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) if (row == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) row = dimm->csrow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) else if (row >= 0 && row != dimm->csrow)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) row = -2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) if (chan == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) chan = dimm->cschannel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) else if (chan >= 0 && chan != dimm->cschannel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) chan = -2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) if (any_memory)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) strcpy(e->label, "any memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) else if (!*e->label)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) strcpy(e->label, "unknown memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) edac_inc_csrow(e, row, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) /* Fill the RAM location data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) p = e->location;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) for (i = 0; i < mci->n_layers; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) if (pos[i] < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) p += sprintf(p, "%s:%d ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) edac_layer_name[mci->layers[i].type],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) pos[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) if (p > e->location)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) *(p - 1) = '\0';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) edac_raw_mc_handle_error(e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) EXPORT_SYMBOL_GPL(edac_mc_handle_error);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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