^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Intel e7xxx Memory Controller kernel module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * (C) 2003 Linux Networx (http://lnxi.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This file may be distributed under the terms of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * GNU General Public License.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * See "enum e7xxx_chips" below for supported chipsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Written by Thayne Harbaugh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Based on work by Dan Hollis <goemon at anime dot net> and others.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * http://www.anime.net/~goemon/linux-ecc/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Datasheet:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * http://www.intel.com/content/www/us/en/chipsets/e7501-chipset-memory-controller-hub-datasheet.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Contributors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Eric Biederman (Linux Networx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Tom Zimmerman (Linux Networx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Jim Garlick (Lawrence Livermore National Labs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Dave Peterson (Lawrence Livermore National Labs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * That One Guy (Some other place)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Wang Zhenyu (intel.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * $Id: edac_e7xxx.c,v 1.5.2.9 2005/10/05 00:43:44 dsp_llnl Exp $
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/pci_ids.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/edac.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "edac_module.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define EDAC_MOD_STR "e7xxx_edac"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define e7xxx_printk(level, fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) edac_printk(level, "e7xxx", fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define e7xxx_mc_printk(mci, level, fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) edac_mc_chipset_printk(mci, level, "e7xxx", fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #ifndef PCI_DEVICE_ID_INTEL_7205_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PCI_DEVICE_ID_INTEL_7205_0 0x255d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #endif /* PCI_DEVICE_ID_INTEL_7205_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #ifndef PCI_DEVICE_ID_INTEL_7205_1_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PCI_DEVICE_ID_INTEL_7205_1_ERR 0x2551
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #endif /* PCI_DEVICE_ID_INTEL_7205_1_ERR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #ifndef PCI_DEVICE_ID_INTEL_7500_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PCI_DEVICE_ID_INTEL_7500_0 0x2540
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #endif /* PCI_DEVICE_ID_INTEL_7500_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #ifndef PCI_DEVICE_ID_INTEL_7500_1_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PCI_DEVICE_ID_INTEL_7500_1_ERR 0x2541
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #endif /* PCI_DEVICE_ID_INTEL_7500_1_ERR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #ifndef PCI_DEVICE_ID_INTEL_7501_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PCI_DEVICE_ID_INTEL_7501_0 0x254c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #endif /* PCI_DEVICE_ID_INTEL_7501_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #ifndef PCI_DEVICE_ID_INTEL_7501_1_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PCI_DEVICE_ID_INTEL_7501_1_ERR 0x2541
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #endif /* PCI_DEVICE_ID_INTEL_7501_1_ERR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #ifndef PCI_DEVICE_ID_INTEL_7505_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PCI_DEVICE_ID_INTEL_7505_0 0x2550
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #endif /* PCI_DEVICE_ID_INTEL_7505_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #ifndef PCI_DEVICE_ID_INTEL_7505_1_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PCI_DEVICE_ID_INTEL_7505_1_ERR 0x2551
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #endif /* PCI_DEVICE_ID_INTEL_7505_1_ERR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define E7XXX_NR_CSROWS 8 /* number of csrows */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define E7XXX_NR_DIMMS 8 /* 2 channels, 4 dimms/channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* E7XXX register addresses - device 0 function 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define E7XXX_DRB 0x60 /* DRAM row boundary register (8b) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define E7XXX_DRA 0x70 /* DRAM row attribute register (8b) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * 31 Device width row 7 0=x8 1=x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * 27 Device width row 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * 23 Device width row 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * 19 Device width row 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * 15 Device width row 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * 11 Device width row 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * 7 Device width row 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * 3 Device width row 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define E7XXX_DRC 0x7C /* DRAM controller mode reg (32b) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * 22 Number channels 0=1,1=2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * 19:18 DRB Granularity 32/64MB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define E7XXX_TOLM 0xC4 /* DRAM top of low memory reg (16b) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define E7XXX_REMAPBASE 0xC6 /* DRAM remap base address reg (16b) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define E7XXX_REMAPLIMIT 0xC8 /* DRAM remap limit address reg (16b) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* E7XXX register addresses - device 0 function 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define E7XXX_DRAM_FERR 0x80 /* DRAM first error register (8b) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define E7XXX_DRAM_NERR 0x82 /* DRAM next error register (8b) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define E7XXX_DRAM_CELOG_ADD 0xA0 /* DRAM first correctable memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* error address register (32b) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * 31:28 Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * 27:6 CE address (4k block 33:12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * 5:0 Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define E7XXX_DRAM_UELOG_ADD 0xB0 /* DRAM first uncorrectable memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* error address register (32b) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * 31:28 Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * 27:6 CE address (4k block 33:12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * 5:0 Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define E7XXX_DRAM_CELOG_SYNDROME 0xD0 /* DRAM first correctable memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* error syndrome register (16b) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) enum e7xxx_chips {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) E7500 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) E7501,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) E7505,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) E7205,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct e7xxx_pvt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct pci_dev *bridge_ck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 tolm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 remapbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 remaplimit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) const struct e7xxx_dev_info *dev_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct e7xxx_dev_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u16 err_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) const char *ctl_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct e7xxx_error_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u8 dram_ferr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u8 dram_nerr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u32 dram_celog_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u16 dram_celog_syndrome;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 dram_uelog_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static struct edac_pci_ctl_info *e7xxx_pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static const struct e7xxx_dev_info e7xxx_devs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) [E7500] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .err_dev = PCI_DEVICE_ID_INTEL_7500_1_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .ctl_name = "E7500"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) [E7501] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .err_dev = PCI_DEVICE_ID_INTEL_7501_1_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .ctl_name = "E7501"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) [E7505] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .err_dev = PCI_DEVICE_ID_INTEL_7505_1_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .ctl_name = "E7505"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) [E7205] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .err_dev = PCI_DEVICE_ID_INTEL_7205_1_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .ctl_name = "E7205"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* FIXME - is this valid for both SECDED and S4ECD4ED? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static inline int e7xxx_find_channel(u16 syndrome)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) edac_dbg(3, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if ((syndrome & 0xff00) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if ((syndrome & 0x00ff) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if ((syndrome & 0xf000) == 0 || (syndrome & 0x0f00) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) unsigned long page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u32 remap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct e7xxx_pvt *pvt = (struct e7xxx_pvt *)mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) edac_dbg(3, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if ((page < pvt->tolm) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ((page >= 0x100000) && (page < pvt->remapbase)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) remap = (page - pvt->tolm) + pvt->remapbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (remap < pvt->remaplimit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return remap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) e7xxx_printk(KERN_ERR, "Invalid page %lx - out of range\n", page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return pvt->tolm - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static void process_ce(struct mem_ctl_info *mci, struct e7xxx_error_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u32 error_1b, page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u16 syndrome;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int row;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) edac_dbg(3, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* read the error address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) error_1b = info->dram_celog_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* FIXME - should use PAGE_SHIFT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) page = error_1b >> 6; /* convert the address to 4k page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* read the syndrome */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) syndrome = info->dram_celog_syndrome;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* FIXME - check for -1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) row = edac_mc_find_csrow_by_page(mci, page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* convert syndrome to channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) channel = e7xxx_find_channel(syndrome);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, page, 0, syndrome,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) row, channel, -1, "e7xxx CE", "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static void process_ce_no_info(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) edac_dbg(3, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0, 0, -1, -1, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) "e7xxx CE log register overflow", "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static void process_ue(struct mem_ctl_info *mci, struct e7xxx_error_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u32 error_2b, block_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int row;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) edac_dbg(3, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* read the error address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) error_2b = info->dram_uelog_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* FIXME - should use PAGE_SHIFT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) block_page = error_2b >> 6; /* convert to 4k address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) row = edac_mc_find_csrow_by_page(mci, block_page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, block_page, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) row, -1, -1, "e7xxx UE", "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static void process_ue_no_info(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) edac_dbg(3, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0, -1, -1, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) "e7xxx UE log register overflow", "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static void e7xxx_get_error_info(struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct e7xxx_error_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct e7xxx_pvt *pvt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) pvt = (struct e7xxx_pvt *)mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_FERR, &info->dram_ferr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_NERR, &info->dram_nerr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if ((info->dram_ferr & 1) || (info->dram_nerr & 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_CELOG_ADD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) &info->dram_celog_add);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) pci_read_config_word(pvt->bridge_ck,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) E7XXX_DRAM_CELOG_SYNDROME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) &info->dram_celog_syndrome);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if ((info->dram_ferr & 2) || (info->dram_nerr & 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_UELOG_ADD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) &info->dram_uelog_add);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (info->dram_ferr & 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_FERR, 0x03, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (info->dram_nerr & 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_NERR, 0x03, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static int e7xxx_process_error_info(struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct e7xxx_error_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) int handle_errors)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) int error_found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) error_found = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* decode and report errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (info->dram_ferr & 1) { /* check first error correctable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) error_found = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (handle_errors)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) process_ce(mci, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (info->dram_ferr & 2) { /* check first error uncorrectable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) error_found = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (handle_errors)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) process_ue(mci, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (info->dram_nerr & 1) { /* check next error correctable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) error_found = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (handle_errors) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (info->dram_ferr & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) process_ce_no_info(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) process_ce(mci, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (info->dram_nerr & 2) { /* check next error uncorrectable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) error_found = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (handle_errors) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (info->dram_ferr & 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) process_ue_no_info(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) process_ue(mci, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return error_found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static void e7xxx_check(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct e7xxx_error_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) edac_dbg(3, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) e7xxx_get_error_info(mci, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) e7xxx_process_error_info(mci, &info, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* Return 1 if dual channel mode is active. Else return 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static inline int dual_channel_active(u32 drc, int dev_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return (dev_idx == E7501) ? ((drc >> 22) & 0x1) : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* Return DRB granularity (0=32mb, 1=64mb). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static inline int drb_granularity(u32 drc, int dev_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* only e7501 can be single channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return (dev_idx == E7501) ? ((drc >> 18) & 0x3) : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static void e7xxx_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) int dev_idx, u32 drc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) unsigned long last_cumul_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) int index, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) u32 dra, cumul_size, nr_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) int drc_chan, drc_drbg, drc_ddim, mem_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct csrow_info *csrow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct dimm_info *dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) enum edac_type edac_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) pci_read_config_dword(pdev, E7XXX_DRA, &dra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) drc_chan = dual_channel_active(drc, dev_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) drc_drbg = drb_granularity(drc, dev_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) drc_ddim = (drc >> 20) & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) last_cumul_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* The dram row boundary (DRB) reg values are boundary address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * for each DRAM row with a granularity of 32 or 64MB (single/dual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * channel operation). DRB regs are cumulative; therefore DRB7 will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * contain the total memory contained in all eight rows.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) for (index = 0; index < mci->nr_csrows; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* mem_dev 0=x8, 1=x4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) mem_dev = (dra >> (index * 4 + 3)) & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) csrow = mci->csrows[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) pci_read_config_byte(pdev, E7XXX_DRB + index, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* convert a 64 or 32 MiB DRB to a page size. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) cumul_size = value << (25 + drc_drbg - PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) edac_dbg(3, "(%d) cumul_size 0x%x\n", index, cumul_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (cumul_size == last_cumul_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) continue; /* not populated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) csrow->first_page = last_cumul_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) csrow->last_page = cumul_size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) nr_pages = cumul_size - last_cumul_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) last_cumul_size = cumul_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * if single channel or x8 devices then SECDED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * if dual channel and x4 then S4ECD4ED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (drc_ddim) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (drc_chan && mem_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) edac_mode = EDAC_S4ECD4ED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) mci->edac_cap |= EDAC_FLAG_S4ECD4ED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) edac_mode = EDAC_SECDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) mci->edac_cap |= EDAC_FLAG_SECDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) edac_mode = EDAC_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) for (j = 0; j < drc_chan + 1; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) dimm = csrow->channels[j]->dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) dimm->nr_pages = nr_pages / (drc_chan + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) dimm->grain = 1 << 12; /* 4KiB - resolution of CELOG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) dimm->mtype = MEM_RDDR; /* only one type supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) dimm->dtype = mem_dev ? DEV_X4 : DEV_X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) dimm->edac_mode = edac_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static int e7xxx_probe1(struct pci_dev *pdev, int dev_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) u16 pci_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct mem_ctl_info *mci = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct edac_mc_layer layers[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct e7xxx_pvt *pvt = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) u32 drc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) int drc_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct e7xxx_error_info discard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) edac_dbg(0, "mci\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) pci_read_config_dword(pdev, E7XXX_DRC, &drc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) drc_chan = dual_channel_active(drc, dev_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * According with the datasheet, this device has a maximum of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * 4 DIMMS per channel, either single-rank or dual-rank. So, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * total amount of dimms is 8 (E7XXX_NR_DIMMS).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * That means that the DIMM is mapped as CSROWs, and the channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * will map the rank. So, an error to either channel should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * attributed to the same dimm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) layers[0].size = E7XXX_NR_CSROWS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) layers[0].is_virt_csrow = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) layers[1].type = EDAC_MC_LAYER_CHANNEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) layers[1].size = drc_chan + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) layers[1].is_virt_csrow = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (mci == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) edac_dbg(3, "init mci\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) mci->mtype_cap = MEM_FLAG_RDDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) EDAC_FLAG_S4ECD4ED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* FIXME - what if different memory types are in different csrows? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) mci->mod_name = EDAC_MOD_STR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) mci->pdev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) edac_dbg(3, "init pvt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) pvt = (struct e7xxx_pvt *)mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) pvt->dev_info = &e7xxx_devs[dev_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) pvt->dev_info->err_dev, pvt->bridge_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (!pvt->bridge_ck) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) e7xxx_printk(KERN_ERR, "error reporting device not found:"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) "vendor %x device 0x%x (broken BIOS?)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) PCI_VENDOR_ID_INTEL, e7xxx_devs[dev_idx].err_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) goto fail0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) edac_dbg(3, "more mci init\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) mci->ctl_name = pvt->dev_info->ctl_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) mci->dev_name = pci_name(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) mci->edac_check = e7xxx_check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) mci->ctl_page_to_phys = ctl_page_to_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) e7xxx_init_csrows(mci, pdev, dev_idx, drc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) mci->edac_cap |= EDAC_FLAG_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) edac_dbg(3, "tolm, remapbase, remaplimit\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* load the top of low memory, remap base, and remap limit vars */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) pci_read_config_word(pdev, E7XXX_TOLM, &pci_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) pvt->tolm = ((u32) pci_data) << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) pci_read_config_word(pdev, E7XXX_REMAPBASE, &pci_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) pvt->remapbase = ((u32) pci_data) << 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) pci_read_config_word(pdev, E7XXX_REMAPLIMIT, &pci_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) pvt->remaplimit = ((u32) pci_data) << 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) e7xxx_printk(KERN_INFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) "tolm = %x, remapbase = %x, remaplimit = %x\n", pvt->tolm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) pvt->remapbase, pvt->remaplimit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* clear any pending errors, or initial state bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) e7xxx_get_error_info(mci, &discard);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* Here we assume that we will never see multiple instances of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * type of memory controller. The ID is therefore hardcoded to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (edac_mc_add_mc(mci)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) edac_dbg(3, "failed edac_mc_add_mc()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) goto fail1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* allocating generic PCI control info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) e7xxx_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (!e7xxx_pci) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) "%s(): Unable to create PCI control\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) "%s(): PCI error report via EDAC not setup\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* get this far and it's successful */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) edac_dbg(3, "success\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) fail1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) pci_dev_put(pvt->bridge_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) fail0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* returns count (>= 0), or negative on error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static int e7xxx_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) edac_dbg(0, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /* wake up and enable device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return pci_enable_device(pdev) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) -EIO : e7xxx_probe1(pdev, ent->driver_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static void e7xxx_remove_one(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct mem_ctl_info *mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct e7xxx_pvt *pvt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) edac_dbg(0, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (e7xxx_pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) edac_pci_release_generic_ctl(e7xxx_pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) pvt = (struct e7xxx_pvt *)mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) pci_dev_put(pvt->bridge_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static const struct pci_device_id e7xxx_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) PCI_VEND_DEV(INTEL, 7205_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) E7205},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) PCI_VEND_DEV(INTEL, 7500_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) E7500},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) PCI_VEND_DEV(INTEL, 7501_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) E7501},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) PCI_VEND_DEV(INTEL, 7505_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) E7505},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) } /* 0 terminated list. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) MODULE_DEVICE_TABLE(pci, e7xxx_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static struct pci_driver e7xxx_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .name = EDAC_MOD_STR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .probe = e7xxx_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .remove = e7xxx_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .id_table = e7xxx_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static int __init e7xxx_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* Ensure that the OPSTATE is set correctly for POLL or NMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) opstate_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return pci_register_driver(&e7xxx_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static void __exit e7xxx_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) pci_unregister_driver(&e7xxx_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) module_init(e7xxx_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) module_exit(e7xxx_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh et al\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) "Based on.work by Dan Hollis et al");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) MODULE_DESCRIPTION("MC support for Intel e7xxx memory controllers");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) module_param(edac_op_state, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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